| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 137 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS))
138 if (Op0->getOpcode() == OpcodeToExpand) {
140 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS;
197 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS);
200 if (!Op0 || Op0->getOpcode() != OpcodeToExtract ||
205 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1);
268 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 100 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
102 if (Value *V = SimplifyMulInst(Op0, Op1, TD))
109 return BinaryOperator::CreateNeg(Op0, I.getName());
114 if (BinaryOperator *SI = dyn_cast<BinaryOperator>(Op0))
122 Constant *NewCst = ConstantInt::get(Op0->getType(), Val.logBase2());
123 BinaryOperator *Shl = BinaryOperator::CreateShl(Op0, NewCst);
131 if (Op0->hasOneUse() &&
132 match(Op0, m_Add(m_Value(X), m_ConstantInt(C1)))) {
146 if (Op0->hasOneUse()) {
149 if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))
[all...] |
| InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
31 if (isa<Constant>(Op0))
37 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I))
312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,
320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) {
322 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n");
325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this));
331 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits();
338 return ReplaceInstUsesWith(I, Constant::getNullValue(Op0->getType()));
345 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0))
[all...] |
| InstCombineAndOrXor.cpp | 714 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1);
717 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder);
[all...] |
| InstCombineCompares.cpp | [all...] |
| InstCombineAddSub.cpp | [all...] |
| InstructionCombining.cpp | 213 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(I.getOperand(0));
218 if (Op0 && Op0->getOpcode() == Opcode) {
219 Value *A = Op0->getOperand(0);
220 Value *B = Op0->getOperand(1);
231 (!Op0 || (isa<BinaryOperator>(Op0) && Op0->hasNoSignedWrap()))) {
233 // the operands to Op0.
269 if (Op0 && Op0->getOpcode() == Opcode)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 188 unsigned Op0, bool Op0IsKill);
197 unsigned Op0, bool Op0IsKill,
207 unsigned Op0, bool Op0IsKill,
217 unsigned Op0, bool Op0IsKill,
227 unsigned Op0, bool Op0IsKill,
237 unsigned Op0, bool Op0IsKill,
267 unsigned Op0, bool Op0IsKill);
274 unsigned Op0, bool Op0IsKill,
282 unsigned Op0, bool Op0IsKill,
291 unsigned Op0, bool Op0IsKill
[all...] |
| /external/llvm/include/llvm/Support/ |
| GetElementPtrTypeIterator.h | 102 gep_type_begin(Type *Op0, ArrayRef<T> A) {
103 return generic_gep_type_iterator<const T *>::begin(Op0, A.begin());
108 gep_type_end(Type *Op0, ArrayRef<T> A) {
|
| PatternMatch.h | 988 m_Intrinsic(const T0 &Op0) {
989 return m_CombineAnd(m_Intrinsic<IntrID>(), m_Argument<0>(Op0));
994 m_Intrinsic(const T0 &Op0, const T1 &Op1) {
995 return m_CombineAnd(m_Intrinsic<IntrID>(Op0), m_Argument<1>(Op1));
1000 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) {
1001 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2));
1006 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
1007 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
1013 m_BSwap(const Opnd0 &Op0) {
1014 return m_Intrinsic<Intrinsic::bswap>(Op0);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 402 unsigned Op0 = getRegForValue(I->getOperand(0));
403 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
427 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
439 ISDOpcode, Op0, Op0IsKill, CF);
457 Op0, Op0IsKill,
777 unsigned Op0 = getRegForValue(I->getOperand(0));
778 if (Op0 == 0)
793 ResultReg).addReg(Op0);
799 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
[all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 192 SDValue Op0, Op1;
196 if (!SelectADDRrr(Op, Op0, Op1))
197 SelectADDRri(Op, Op0, Op1);
201 OutOps.push_back(Op0);
|
| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | 554 Constant *Op0 = CE->getOperand(0);
558 GenericValue Result = getConstantValue(Op0);
567 GenericValue GV = getConstantValue(Op0);
573 GenericValue GV = getConstantValue(Op0);
579 GenericValue GV = getConstantValue(Op0);
586 GenericValue GV = getConstantValue(Op0);
592 GenericValue GV = getConstantValue(Op0);
597 GenericValue GV = getConstantValue(Op0);
612 GenericValue GV = getConstantValue(Op0);
628 GenericValue GV = getConstantValue(Op0);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/include/llvm/Analysis/ |
| InstructionSimplify.h | 128 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW,
135 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact,
142 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
|
| ScalarEvolution.h | 584 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
587 Ops.push_back(Op0);
602 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
605 Ops.push_back(Op0);
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CorrelatedValuePropagation.cpp | 163 Value *Op0 = C->getOperand(0);
164 if (isa<Instruction>(Op0) &&
165 cast<Instruction>(Op0)->getParent() == C->getParent())
|
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMFastISel.cpp | 108 unsigned Op0, bool Op0IsKill);
111 unsigned Op0, bool Op0IsKill,
115 unsigned Op0, bool Op0IsKill,
120 unsigned Op0, bool Op0IsKill,
124 unsigned Op0, bool Op0IsKill,
128 unsigned Op0, bool Op0IsKill,
139 unsigned Op0, bool Op0IsKill,
304 unsigned Op0, bool Op0IsKill) {
310 .addReg(Op0, Op0IsKill * RegState::Kill));
313 .addReg(Op0, Op0IsKill * RegState::Kill))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 224 MachineOperand &Op0 = MI->getOperand(0);
225 unsigned Reg0 = Op0.getReg();
228 // Handle instructions that have a prediate register in op0
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 492 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits
502 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
508 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
530 uint32_t Op0 = (Bits >> 14) & 0x3;
538 if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
543 assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
|
| /external/llvm/lib/IR/ |
| AutoUpgrade.cpp | 272 Value *Op0 = CI->getArgOperand(0);
293 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs));
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 288 SDValue Op0, Op1;
292 if (!SelectAddr(Op, Op0, Op1))
297 OutOps.push_back(Op0);
|
