| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 236 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
248 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
254 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
263 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
342 unsigned Op1, Op2;
343 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
347 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
355 unsigned Op1, Op2;
356 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
360 Inst.addOperand(MCOperand::CreateImm(Op1));
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 100 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
102 if (Value *V = SimplifyMulInst(Op0, Op1, TD))
108 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X
111 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
163 if (isa<Constant>(Op1)) {
175 if (Value *Op1v = dyn_castNegVal(Op1))
181 Value *Op1C = Op1;
187 BO = dyn_cast<BinaryOperator>(Op1);
219 return BinaryOperator::CreateAnd(Op0, Op1);
226 return BinaryOperator::CreateShl(Op1, Y)
[all...] |
| InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
32 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
36 if (ConstantInt *CUI = dyn_cast<ConstantInt>(Op1))
44 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) {
48 Op1->getName());
312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,
320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) {
325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this));
336 if (Op1->uge(TypeBits))
[all...] |
| InstCombineCompares.cpp | [all...] |
| InstCombineAddSub.cpp | [all...] |
| InstCombineAndOrXor.cpp | 714 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1);
717 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder);
[all...] |
| InstructionCombining.cpp | 214 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(I.getOperand(1));
247 if (Op1 && Op1->getOpcode() == Opcode) {
249 Value *B = Op1->getOperand(0);
250 Value *C = Op1->getOperand(1);
289 if (Op1 && Op1->getOpcode() == Opcode) {
291 Value *B = Op1->getOperand(0);
292 Value *C = Op1->getOperand(1);
310 if (Op0 && Op1 &
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 160 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS))
161 if (Op1->getOpcode() == OpcodeToExpand) {
163 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1);
198 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS);
201 !Op1 || Op1->getOpcode() != OpcodeToExtract)
206 Value *C = Op1->getOperand(0), *D = Op1->getOperand(1);
269 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)
[all...] |
| ConstantFolding.cpp | 539 /// SymbolicallyEvaluateBinop - One of Op0/Op1 is a constant expression.
544 Constant *Op1, const DataLayout *DL){
557 ComputeMaskedBits(Op1, KnownZero1, KnownOne1, DL);
563 // All the bits of Op1 that the 'and' could be masking are already zero.
564 return Op1;
583 if (IsConstantOffsetFromGlobal(Op1, GV2, Offs2, *DL) &&
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2,
76 SDValue Op1, SDValue Op2,
92 SDValue Op1, SDValue Op2,
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 60 SDValue Op1, SDValue Op2,
|
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 198 unsigned Op1, bool Op1IsKill);
228 unsigned Op1, bool Op1IsKill,
275 unsigned Op1, bool Op1IsKill);
283 unsigned Op1, bool Op1IsKill,
316 unsigned Op1, bool Op1IsKill,
325 unsigned Op1, bool Op1IsKill,
|
| SelectionDAG.h | 530 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
535 Ops.push_back(Op1);
[all...] |
| ISDOpcodes.h | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 192 SDValue Op0, Op1;
196 if (!SelectADDRrr(Op, Op0, Op1))
197 SelectADDRri(Op, Op0, Op1);
202 OutOps.push_back(Op1);
|
| /external/llvm/lib/Transforms/Scalar/ |
| CorrelatedValuePropagation.cpp | 168 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1));
169 if (!Op1) return false;
175 C->getOperand(0), Op1, *PI, C->getParent());
181 C->getOperand(0), Op1, *PI, C->getParent());
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 580 SDValue Op1 = Op.getOperand(1);
584 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
602 assert(MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits()
619 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
626 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
628 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
659 SDValue Op1 = Op.getOperand(1);
676 assert(VT.getSizeInBits() == Op1.getValueType().getSizeInBits(
[all...] |
| FastISel.cpp | 386 unsigned Op1 = getRegForValue(I->getOperand(1));
387 if (Op1 == 0) return false;
391 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
447 unsigned Op1 = getRegForValue(I->getOperand(1));
448 if (Op1 == 0)
458 Op1, Op1IsKill);
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| InstructionSimplify.h | 128 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW,
135 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact,
142 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
|
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 405 SDValue Op1 = N->getOperand(1);
410 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO);
417 unsigned Op1Opc = Op1.getOpcode();
427 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
428 Op1.getOperand(0).getOpcode() != ISD::SRL) {
429 std::swap(Op0, Op1);
435 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
436 Op1.getOperand(0).getOpcode() != ISD::SRL) {
437 std::swap(Op0, Op1);
448 isInt32Immediate(Op1.getOperand(1), Value))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 339 SDValue Op1 = N->getOperand(1);
394 if (SelectDirectAddr(Op1, Addr)) {
427 SelectADDRsi64(Op1.getNode(), Op1, Base, Offset):
428 SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
461 SelectADDRri64(Op1.getNode(), Op1, Base, Offset):
462 SelectADDRri(Op1.getNode(), Op1, Base, Offset))
[all...] |
| /external/llvm/lib/DebugInfo/ |
| DWARFDebugFrame.cpp | 110 uint64_t Op1 = Opcode & DWARF_CFI_PRIMARY_OPERAND_MASK;
115 addInstruction(Primary, Op1);
118 addInstruction(Primary, Op1, Data.getULEB128(Offset));
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 275 MachineOperand Op1 = MI->getOperand(S1);
278 ChangeOpInto(MI->getOperand(S2), Op1);
|
