| /frameworks/opt/vcard/tests/src/com/android/vcard/tests/ |
| VCardParserTests.java | 37 private enum Order {
46 private final List<Order> mHistory = new ArrayList<Order>();
47 private final List<Order> mExpectedOrder = new ArrayList<Order>();
49 public MockVCardInterpreter addExpectedOrder(Order order) {
50 mExpectedOrder.add(order);
54 private void inspectOrder(Order order) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
36 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
49 assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() &&
50 "Target hint is outside allocation order.");
|
| AllocationOrder.h | 1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
30 ArrayRef<MCPhysReg> Order;
42 /// Get the allocation order without reordered hints.
43 ArrayRef<MCPhysReg> getOrder() const { return Order; }
45 /// Return the next physical register in the allocation order, or 0.
51 while (Pos < int(Order.size())) {
52 unsigned Reg = Order[Pos++];
60 /// Limit'th register in the RegisterClassInfo allocation order
[all...] |
| RegisterClassInfo.cpp | 72 /// compute - Compute the preferred allocation order for RC with reserved
74 /// aliases ordered according to the CSR order specified by the target.
81 if (!RCI.Order)
82 RCI.Order.reset(new MCPhysReg[NumRegs]);
91 // allocation order, we can simply use begin/end here.
95 // Remove reserved registers from the allocation order.
107 RCI.Order[N++] = PhysReg;
112 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
114 // CSR aliases go after the volatile registers, preserve the target's order.
120 RCI.Order[N++] = PhysReg
[all...] |
| TargetRegisterInfo.cpp | 123 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
124 for (unsigned i = 0; i != Order.size(); ++i)
125 R.set(Order[i]);
255 ArrayRef<MCPhysReg> Order,
277 // Check that Phys is in the allocation order. We shouldn't heed hints
278 // from VirtReg's register class if they aren't in the allocation order. The
280 if (std::find(Order.begin(), Order.end(), Phys) == Order.end())
|
| RegAllocGreedy.cpp | 410 // Everything is allocated in long->short order. Long ranges that don't fit
437 AllocationOrder &Order,
439 Order.rewind();
441 while ((PhysReg = Order.next()))
444 if (!PhysReg || Order.isHint())
452 if (Order.isHint(Hint)) {
470 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
480 /// eviction policy defined by this function together with the allocation order
550 // larger allocation order.
623 /// @param Order Physregs to try
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 50 unsigned Order;
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
101 // Returns the SDNodeOrder. This is the order of the preceding node in the
103 unsigned getOrder() { return Order; }
|
| ScheduleDAGSDNodes.cpp | 205 /// outputs to ensure they are scheduled together and in order. This
245 // Sort them in increasing order.
267 // ensure they are scheduled in order of increasing addresses.
324 // Add all nodes in depth first order.
707 unsigned Order) {
712 // order number right after the N.
720 if (!Order || DVOrder == ++Order) {
731 // ProcessSourceNode - Process nodes with source order numbers. These are added
733 // instructions in the right order
[all...] |
| /external/aac/libAACdec/src/ |
| aacdec_tns.h | 99 TNS_MAXIMUM_ORDER = 20, /* 12 for AAC-LC and AAC-SSR. Set to 20 for AAC-Main (AOT 1). Some broken encoders also do order 20 for AAC-LC :( */
113 UCHAR Order;
|
| aacdec_tns.cpp | 133 UCHAR n_filt,order; local
176 filter->Order = order = (UCHAR) FDKreadBits(bs, isLongFlag ? 5 : 3);
179 if (filter->Order > TNS_MAXIMUM_ORDER){
180 filter->Order = order = TNS_MAXIMUM_ORDER;
183 if (order)
200 for (i=0; i < order; i++)
216 static void CTns_Filter (FIXP_DBL *spec, int size, int inc, FIXP_TCC coeff [], int order)
218 // - Simple all-pole filter of order "order" defined b
[all...] |
| /external/llvm/test/MC/COFF/ |
| symbol-alias.s | 26 # Order is important here. Assign _bar_alias_alias before _bar_alias.
|
| /external/icu4c/test/intltest/ |
| tscoll.h | 26 struct Order
28 int32_t order; member in struct:IntlTestCollator::Order
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
|
| tscoll.cpp | 408 LocalArray<Order> orders(getOrders(iter, orderLength));
433 if (o != orders[index].order) {
437 while (index > 0 && orders[--index].order == 0) {
441 if (o != orders[index].order) {
442 errln("Mismatched order at index %d: 0x%0:8X vs. 0x%0:8X", index,
443 orders[index].order, o);
461 while (index != 0 && orders[index - 1].order == 0)
501 IntlTestCollator::Order *IntlTestCollator::getOrders(CollationElementIterator &iter, int32_t &orderLength)
505 LocalArray<Order> orders(new Order[maxSize])
509 int32_t order; local
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 34 OwningArrayPtr<MCPhysReg> Order;
41 return makeArrayRef(Order.get(), NumRegs);
89 /// getOrder - Returns the preferred allocation order for RC. The order
115 /// Get the minimum register cost in RC's allocation order.
|
| ScheduleDAG.h | 52 Order ///< Any other ordering dependency.
85 /// Order - Additional information about Order dependencies.
126 : Dep(S, Order), Contents(), Latency(0), MinLatency(0) {
138 case Order:
198 /// isNormalMemory - Test if this is an Order dependence between two
202 return getKind() == Order && (Contents.OrdKind == MayAliasMem
206 /// isMustAlias - Test if this is an Order dependence that is marked
210 return getKind() == Order && Contents.OrdKind == MustAliasMem;
218 return getKind() == Order && Contents.OrdKind >= Weak
[all...] |
| /external/webkit/LayoutTests/http/conf/ |
| apache2-debian-httpd.conf | 188 # Note: The order in which modules are loaded is important. Don't change
189 # the order below without expert advice.
295 Order allow,deny
317 Order allow,deny
327 Order allow,deny
333 Order allow,deny
524 # Just list the languages in decreasing order of preference. We have
637 # Order deny,allow
|
| apache2-httpd.conf | 184 # Note: The order in which modules are loaded is important. Don't change
185 # the order below without expert advice.
316 Order allow,deny
338 Order allow,deny
348 Order allow,deny
354 Order allow,deny
545 # Just list the languages in decreasing order of preference. We have
658 # Order deny,allow
|
| apache2-msys-httpd.conf | 184 # Note: The order in which modules are loaded is important. Don't change
185 # the order below without expert advice.
317 Order allow,deny
339 Order allow,deny
349 Order allow,deny
355 Order allow,deny
546 # Just list the languages in decreasing order of preference. We have
659 # Order deny,allow
|
| cygwin-httpd.conf | 93 # in that order. The latter two files are now distributed empty, as it is
198 # Note: The order in which modules are loaded is important. Don't change
199 # the order below without expert advice.
242 # (static and shared ones) to achieve correct module execution order.
348 Order allow,deny
370 Order allow,deny
380 Order allow,deny
386 Order allow,deny
577 # Just list the languages in decreasing order of preference. We have
690 # Order deny,allo
[all...] |
| fedora-httpd.conf | 336 Order allow,deny
350 # Order allow,deny
354 # Order deny,allow
381 Order allow,deny
391 Order allow,deny
397 Order allow,deny
629 # Just list the languages in decreasing order of preference. We have
778 # Order deny,allow
790 # Order deny,allow
803 # Order deny,allo
[all...] |
| httpd.conf | 93 # in that order. The latter two files are now distributed empty, as it is
200 # Note: The order in which modules are loaded is important. Don't change
201 # the order below without expert advice.
245 # (static and shared ones) to achieve correct module execution order.
351 Order allow,deny
373 Order allow,deny
383 Order allow,deny
389 Order allow,deny
580 # Just list the languages in decreasing order of preference. We have
693 # Order deny,allo
[all...] |
| /external/clang/lib/CodeGen/ |
| CGAtomic.cpp | 186 uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) {
205 CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order);
218 Load->setAtomic(Order);
233 Store->setAtomic(Order);
296 CGF.Builder.CreateAtomicRMW(Op, Ptr, LoadVal1, Order);
334 llvm::Value *Ptr, *Order, *OrderFail = 0, *Val1 = 0, *Val2 = 0;
344 Order = EmitScalarExpr(E->getOrder());
455 Args.add(RValue::get(Order),
457 Order = OrderFail;
460 // int order)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUStructurizeCFG.cpp | 179 RNVector Order;
280 /// \brief Build up the general order of nodes
284 for (Order.clear(); I != E; ++I) {
286 Order.append(Nodes.begin(), Nodes.end());
438 for (RNVector::reverse_iterator OI = Order.rbegin(), OE = Order.rend();
642 BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() :
643 Order.back()->getEntry();
676 if (Order.empty() && ExitUseAllowed) {
726 /// Take one node from the order vector and wire it u
[all...] |
| /external/eigen/unsupported/Eigen/src/Splines/ |
| Spline.h | 94 * \brief Evaluation of spline derivatives of up-to given order.
100 * for i ranging between 0 and order.
103 * \param order The order up to which the derivatives are computed.
106 derivatives(Scalar u, DenseIndex order) const;
115 derivatives(Scalar u, DenseIndex order = DerivativeOrder) const;
137 * \brief Computes the non-zero spline basis function derivatives up to given order.
143 * with i ranging from 0 up to the specified order.
147 * \param order The order up to which the basis function derivatives are computes
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 177 ArrayRef<MCPhysReg> Order,
193 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
209 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end())
213 for (unsigned I = 0, E = Order.size(); I != E; ++I) {
214 unsigned Reg = Order[I];
|
