| /external/marisa-trie/v0_1_5/tests/ |
| vector-test.cc | 9 #include <marisa_alpha/bitvector.h>
215 marisa_alpha::BitVector bv;
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| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 61 const BitVector &RR = MF->getRegInfo().getReservedRegs();
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| LiveRangeCalc.h | 25 #include "llvm/ADT/BitVector.h"
47 BitVector Seen;
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| DeadMachineInstructionElim.cpp | 35 BitVector LivePhysRegs;
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| MachineLICM.cpp | 172 BitVector &PhysRegDefs,
173 BitVector &PhysRegClobbers,
404 BitVector &PhysRegDefs,
405 BitVector &PhysRegClobbers,
497 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
498 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
533 BitVector TermRegs(NumRegs);
[all...] |
| PostRASchedulerList.cpp | 26 #include "llvm/ADT/BitVector.h"
125 BitVector LiveRegs;
473 BitVector killedRegs(TRI->getNumRegs());
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| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 101 BitVector getReservedRegs(const MachineFunction &MF) const;
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| ARMBaseRegisterInfo.cpp | 21 #include "llvm/ADT/BitVector.h"
82 BitVector ARMBaseRegisterInfo::
87 BitVector Reserved(getNumRegs());
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| /external/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 23 #include "llvm/ADT/BitVector.h"
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| MipsSERegisterInfo.cpp | 21 #include "llvm/ADT/BitVector.h"
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| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 109 BitVector getReservedRegs(const MachineFunction &MF) const;
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| X86RegisterInfo.cpp | 22 #include "llvm/ADT/BitVector.h"
304 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
305 BitVector Reserved(getNumRegs());
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| /external/clang/lib/Analysis/ |
| UninitializedValues.cpp | 209 llvm::BitVector enqueuedBlocks;
731 llvm::BitVector &wasAnalyzed,
768 llvm::BitVector hadUse;
819 llvm::BitVector previouslyVisited(cfg.getNumBlockIDs());
821 llvm::BitVector wasAnalyzed(cfg.getNumBlockIDs(), false);
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| /external/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 17 #include "llvm/ADT/BitVector.h"
88 BitVector UsedRegUnits;
94 BitVector UsedPhysRegMask;
100 BitVector ReservedRegs;
440 const BitVector &getReservedRegs() const {
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| LiveIntervalAnalysis.h | 23 #include "llvm/ADT/BitVector.h"
340 BitVector &UsableRegs);
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| ScheduleDAG.h | 19 #include "llvm/ADT/BitVector.h"
705 BitVector Visited;
714 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
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| /external/v8/src/ |
| hydrogen-instructions.cc | [all...] |
| hydrogen.h | 44 class BitVector;
338 BitVector* visited,
342 BitVector* visited,
350 void PropagateMinusZeroChecks(HValue* value, BitVector* visited);
[all...] |
| /dalvik/vm/analysis/ |
| CodeVerify.h | 141 BitVector* liveRegs;
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| /sdk/emulator/qtools/ |
| check_stack.cpp | 9 #include "bitvector.h"
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| q2dm.cpp | 9 #include "bitvector.h"
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| /external/llvm/include/llvm/ADT/ |
| SparseMultiSet.h | 43 /// Compared to BitVector, SparseMultiSet<unsigned> uses 8x-40x more memory, but
327 /// This is not the same as BitVector::empty().
333 /// This is not the same as BitVector::size() which returns the size of the
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 22 #include "llvm/ADT/BitVector.h"
102 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
103 BitVector Reserved(getNumRegs());
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| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 19 #include "llvm/ADT/BitVector.h"
516 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
519 const BitVector &Bits,
533 BitVector Values;
[all...] |
| /external/srtp/googlepatches/ |
| vidyo-3-srtp-ws.patch | 240 + /* initialize bitvector to zero */
348 - /* initialize bitvector to zero */
457 - /* if the length is greater than the bitvector, return an error */
|
