1 //===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef X86REGISTERINFO_H 15 #define X86REGISTERINFO_H 16 17 #include "llvm/Target/TargetRegisterInfo.h" 18 19 #define GET_REGINFO_HEADER 20 #include "X86GenRegisterInfo.inc" 21 22 namespace llvm { 23 class Type; 24 class TargetInstrInfo; 25 class X86TargetMachine; 26 27 class X86RegisterInfo : public X86GenRegisterInfo { 28 public: 29 X86TargetMachine &TM; 30 const TargetInstrInfo &TII; 31 32 private: 33 /// Is64Bit - Is the target 64-bits. 34 /// 35 bool Is64Bit; 36 37 /// IsWin64 - Is the target on of win64 flavours 38 /// 39 bool IsWin64; 40 41 /// SlotSize - Stack slot size in bytes. 42 /// 43 unsigned SlotSize; 44 45 /// StackPtr - X86 physical register used as stack ptr. 46 /// 47 unsigned StackPtr; 48 49 /// FramePtr - X86 physical register used as frame ptr. 50 /// 51 unsigned FramePtr; 52 53 /// BasePtr - X86 physical register used as a base ptr in complex stack 54 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to 55 /// variable size stack objects. 56 unsigned BasePtr; 57 58 public: 59 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii); 60 61 // FIXME: This should be tablegen'd like getDwarfRegNum is 62 int getSEHRegNum(unsigned i) const; 63 64 /// getCompactUnwindRegNum - This function maps the register to the number for 65 /// compact unwind encoding. Return -1 if the register isn't valid. 66 int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const; 67 68 /// Code Generation virtual methods... 69 /// 70 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; 71 72 /// getMatchingSuperRegClass - Return a subclass of the specified register 73 /// class A so that each register in it has a sub-register of the 74 /// specified sub-register index which is in the specified register class B. 75 virtual const TargetRegisterClass * 76 getMatchingSuperRegClass(const TargetRegisterClass *A, 77 const TargetRegisterClass *B, unsigned Idx) const; 78 79 virtual const TargetRegisterClass * 80 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const; 81 82 const TargetRegisterClass* 83 getLargestLegalSuperClass(const TargetRegisterClass *RC) const; 84 85 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 86 /// values. 87 const TargetRegisterClass * 88 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const; 89 90 /// getCrossCopyRegClass - Returns a legal register class to copy a register 91 /// in the specified class to or from. Returns NULL if it is possible to copy 92 /// between a two registers of the specified class. 93 const TargetRegisterClass * 94 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 95 96 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 97 MachineFunction &MF) const; 98 99 /// getCalleeSavedRegs - Return a null-terminated list of all of the 100 /// callee-save registers on this target. 101 const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const; 102 const uint32_t *getCallPreservedMask(CallingConv::ID) const; 103 const uint32_t *getNoPreservedMask() const; 104 105 /// getReservedRegs - Returns a bitset indexed by physical register number 106 /// indicating if a register is a special register that has particular uses and 107 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 108 /// register scavenger to determine what registers are free. 109 BitVector getReservedRegs(const MachineFunction &MF) const; 110 111 bool hasBasePointer(const MachineFunction &MF) const; 112 113 bool canRealignStack(const MachineFunction &MF) const; 114 115 bool needsStackRealignment(const MachineFunction &MF) const; 116 117 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 118 int &FrameIdx) const; 119 120 void eliminateFrameIndex(MachineBasicBlock::iterator MI, 121 int SPAdj, unsigned FIOperandNum, 122 RegScavenger *RS = NULL) const; 123 124 // Debug information queries. 125 unsigned getFrameRegister(const MachineFunction &MF) const; 126 unsigned getStackRegister() const { return StackPtr; } 127 unsigned getBaseRegister() const { return BasePtr; } 128 // FIXME: Move to FrameInfok 129 unsigned getSlotSize() const { return SlotSize; } 130 131 // Exception handling queries. 132 unsigned getEHExceptionRegister() const; 133 unsigned getEHHandlerRegister() const; 134 }; 135 136 // getX86SubSuperRegister - X86 utility function. It returns the sub or super 137 // register of a specific X86 register. 138 // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX 139 unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false); 140 141 } // End llvm namespace 142 143 #endif 144
