| /external/clang/lib/ARCMigrate/ |
| TransZeroOutPropsInDealloc.cpp | 164 if (BOE->getOpcode() == BO_Comma)
168 if (BOE->getOpcode() != BO_Assign)
198 if (BO->getOpcode() != BO_Assign) return false;
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleConstraintManager.cpp | 32 switch (SIE->getOpcode()) {
189 BinaryOperator::Opcode op = SE->getOpcode();
220 BinaryOperator::Opcode Op = SE->getOpcode();
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| EscapeAnalysis.java | 219 int op = insn.getOpcode().getOpcode();
255 int prevOpcode = prevSsaInsn.getOpcode().getOpcode();
336 Rop useOpcode = use.getOpcode();
394 int useOpcode = use.getOpcode().getOpcode();
573 switch (use.getOpcode().getOpcode()) {
650 if (insn == null || insn.getOpcode() == null |
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 223 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
230 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
238 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 209 if (MInst->getOpcode() == TargetOpcode::DBG_VALUE ||
210 MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) {
232 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
|
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCCodeEmitter.cpp | 136 switch (MI.getOpcode()) {
160 switch (MI.getOpcode()) {
180 unsigned Opcode = MI.getOpcode();
|
| /external/llvm/lib/Target/Sparc/ |
| SparcAsmPrinter.cpp | 76 if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) {
79 } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri) &&
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 43 switch (N->getOpcode()) {
169 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
182 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
196 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
315 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
333 if (N->getOpcode() == ISD::CTTZ) {
341 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
353 unsigned NewOpc = N->getOpcode();
360 if (N->getOpcode() == ISD::FP_TO_UINT &&
370 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT
[all...] |
| SelectionDAG.cpp | 100 if (N->getOpcode() == ISD::BITCAST)
103 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
108 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
138 N->getOperand(i).getOpcode() != ISD::UNDEF)
148 if (N->getOpcode() == ISD::BITCAST)
151 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
156 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
178 N->getOperand(i).getOpcode() != ISD::UNDEF)
187 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR)
190 if (N->getOpcode() != ISD::BUILD_VECTOR
[all...] |
| SelectionDAGDumper.cpp | 34 switch (getOpcode()) {
36 if (getOpcode() < ISD::BUILTIN_OP_END)
43 return "<<Unknown Machine Node #" + utostr(getOpcode()) + ">>";
47 const char *Name = TLI.getTargetNodeName(getOpcode());
49 return "<<Unknown Target Node #" + utostr(getOpcode()) + ">>";
51 return "<<Unknown Node #" + utostr(getOpcode()) + ">>";
109 unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
|
| LegalizeVectorTypes.cpp | 39 switch (N->getOpcode()) {
131 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
139 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
230 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
237 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
319 if (Arg.getOpcode() == ISD::UNDEF)
357 switch (N->getOpcode()) {
415 Ops[0] = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
485 switch (N->getOpcode()) {
592 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo)
[all...] |
| SelectionDAGISel.cpp | 461 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
546 if (N->getOpcode() != ISD::CopyToReg)
785 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 76 if (Vec.getOpcode() == ISD::UNDEF)
89 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 if (Vec.getOpcode() == ISD::UNDEF)
[all...] |
| X86MCInstLower.cpp | 335 OutMI.setOpcode(MI->getOpcode());
378 switch (OutMI.getOpcode()) {
427 switch (OutMI.getOpcode()) {
451 switch (OutMI.getOpcode()) {
467 unsigned Opcode = OutMI.getOpcode();
487 switch (OutMI.getOpcode()) {
619 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
620 MI.getOpcode() == X86::TLS_base_addr64;
622 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
630 switch (MI.getOpcode()) {
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| OutputFinisher.java | 379 result[i] = insns.get(i).getOpcode();
524 Dop result = findOpcodeForInsn(insn.getLowRegVersion(), insn.getOpcode());
566 Dop originalOpcode = insn.getOpcode();
599 Dop originalOpcode = insn.getOpcode();
689 Dop opcode = insn.getOpcode();
|
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 190 unsigned Opcode = MCID.getOpcode();
220 if (TII->isFpMLxInstruction(DefMI->getOpcode())) {
237 return isFpMulInstruction(DefMI->getOpcode()) || hasLoopHazard(MI);
255 if (TII->canCauseFpMLxStall(NextMI->getOpcode())) {
361 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
|
| ARMConstantIslandPass.cpp | 602 assert(CPEMI && CPEMI->getOpcode() == ARM::CONSTPOOL_ENTRY);
625 if (I->isBranch() && I->getOpcode() == ARM::t2BR_JT)
667 int Opc = I->getOpcode();
816 if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
[all...] |
| Thumb2SizeReduction.cpp | 307 unsigned Opc = MI->getOpcode();
503 unsigned Opc = MI->getOpcode();
619 if (MI->getOpcode() == ARM::t2MUL) {
802 if ((MCID.getOpcode() == ARM::t2RSBSri ||
803 MCID.getOpcode() == ARM::t2RSBri ||
804 MCID.getOpcode() == ARM::t2SXTB ||
805 MCID.getOpcode() == ARM::t2SXTH ||
806 MCID.getOpcode() == ARM::t2UXTB ||
807 MCID.getOpcode() == ARM::t2UXTH) && i == 2)
870 unsigned Opcode = MI->getOpcode();
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 107 switch (MI->getOpcode()) {
163 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
165 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
263 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
264 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
273 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
276 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
277 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
312 switch (Op.getOpcode()) {
352 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
[all...] |
| /external/llvm/lib/IR/ |
| Instruction.cpp | 272 if (getOpcode() != I->getOpcode() ||
338 if (getOpcode() != I->getOpcode() ||
421 switch (getOpcode()) {
441 switch (getOpcode()) {
482 unsigned Opcode = getOpcode();
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | 44 if (I->getOpcode() == Instruction::Shl) {
51 if (I->getOpcode() == Instruction::Mul) {
58 if (I->getOpcode() == Instruction::Add) {
173 unsigned Opc = I->getOpcode();
245 Instruction::CastOps firstOp = Instruction::CastOps(CI->getOpcode());
298 isEliminableCastPair(CSrc, CI.getOpcode(), CI.getType(), TD)) {
355 unsigned Opc = I->getOpcode();
668 unsigned Opc = I->getOpcode(), Tmp;
[all...] |
| InstCombinePHI.cpp | 27 unsigned Opc = FirstInst->getOpcode();
46 if (!I || I->getOpcode() != Opc || !I->hasOneUse() ||
114 CmpInst *NewCI = CmpInst::Create(CIOp->getOpcode(), CIOp->getPredicate(),
122 BinaryOperator::Create(BinOp->getOpcode(), LHSVal, RHSVal);
484 CastInst *NewCI = CastInst::Create(FirstCI->getOpcode(), PhiVal,
491 BinOp = BinaryOperator::Create(BinOp->getOpcode(), PhiVal, ConstantOp);
500 CmpInst *NewCI = CmpInst::Create(CIOp->getOpcode(), CIOp->getPredicate(),
673 if (User->getOpcode() != Instruction::LShr ||
802 cast<Instruction>(PN.getIncomingValue(0))->getOpcode() ==
803 cast<Instruction>(PN.getIncomingValue(1))->getOpcode() &
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | 235 if (CE->getOpcode() == Instruction::PtrToInt ||
236 CE->getOpcode() == Instruction::BitCast)
368 if (CE->getOpcode() == Instruction::IntToPtr &&
468 if (CE->getOpcode() == Instruction::GetElementPtr) {
671 if (CE && CE->getOpcode() == Instruction::Sub &&
716 if (CE->getOpcode() == Instruction::IntToPtr)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 172 switch (Op.getOpcode())
203 switch (N->getOpcode()) {
357 if (Addr.getOpcode() != ISD::ADD) {
367 if (Base.getOpcode() == ISD::ADD &&
368 Base.getOperand(1).getOpcode() == ISD::SHL) {
381 if (Root->getOpcode() == XCoreISD::DPRelativeWrapper ||
382 Root->getOpcode() == XCoreISD::CPRelativeWrapper) {
565 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
582 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
605 if (Op.getOpcode() != ISD::ADD
[all...] |
