1 //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to 11 // JIT-compile bitcode to native PowerPC. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPC.h" 16 #include "PPCRelocations.h" 17 #include "PPCTargetMachine.h" 18 #include "llvm/CodeGen/JITCodeEmitter.h" 19 #include "llvm/CodeGen/MachineFunctionPass.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineModuleInfo.h" 22 #include "llvm/IR/Module.h" 23 #include "llvm/PassManager.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include "llvm/Target/TargetOptions.h" 27 using namespace llvm; 28 29 namespace { 30 class PPCCodeEmitter : public MachineFunctionPass { 31 TargetMachine &TM; 32 JITCodeEmitter &MCE; 33 MachineModuleInfo *MMI; 34 35 void getAnalysisUsage(AnalysisUsage &AU) const { 36 AU.addRequired<MachineModuleInfo>(); 37 MachineFunctionPass::getAnalysisUsage(AU); 38 } 39 40 static char ID; 41 42 /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record 43 /// its address in the function into this pointer. 44 void *MovePCtoLROffset; 45 public: 46 47 PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 48 : MachineFunctionPass(ID), TM(tm), MCE(mce) {} 49 50 /// getBinaryCodeForInstr - This function, generated by the 51 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 52 /// machine instructions. 53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 54 55 56 MachineRelocation GetRelocation(const MachineOperand &MO, 57 unsigned RelocID) const; 58 59 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr 60 unsigned getMachineOpValue(const MachineInstr &MI, 61 const MachineOperand &MO) const; 62 63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const; 64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const; 65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const; 66 67 unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const; 68 unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const; 69 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const; 70 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const; 71 unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const; 72 73 const char *getPassName() const { return "PowerPC Machine Code Emitter"; } 74 75 /// runOnMachineFunction - emits the given MachineFunction to memory 76 /// 77 bool runOnMachineFunction(MachineFunction &MF); 78 79 /// emitBasicBlock - emits the given MachineBasicBlock to memory 80 /// 81 void emitBasicBlock(MachineBasicBlock &MBB); 82 }; 83 } 84 85 char PPCCodeEmitter::ID = 0; 86 87 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code 88 /// to the specified MCE object. 89 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM, 90 JITCodeEmitter &JCE) { 91 return new PPCCodeEmitter(TM, JCE); 92 } 93 94 bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 95 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 96 MF.getTarget().getRelocationModel() != Reloc::Static) && 97 "JIT relocation model must be set to static or default!"); 98 99 MMI = &getAnalysis<MachineModuleInfo>(); 100 MCE.setModuleInfo(MMI); 101 do { 102 MovePCtoLROffset = 0; 103 MCE.startFunction(MF); 104 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) 105 emitBasicBlock(*BB); 106 } while (MCE.finishFunction(MF)); 107 108 return false; 109 } 110 111 void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { 112 MCE.StartMachineBasicBlock(&MBB); 113 114 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ 115 const MachineInstr &MI = *I; 116 MCE.processDebugLoc(MI.getDebugLoc(), true); 117 switch (MI.getOpcode()) { 118 default: 119 MCE.emitWordBE(getBinaryCodeForInstr(MI)); 120 break; 121 case TargetOpcode::PROLOG_LABEL: 122 case TargetOpcode::EH_LABEL: 123 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 124 break; 125 case TargetOpcode::IMPLICIT_DEF: 126 case TargetOpcode::KILL: 127 break; // pseudo opcode, no side effects 128 case PPC::MovePCtoLR: 129 case PPC::MovePCtoLR8: 130 assert(TM.getRelocationModel() == Reloc::PIC_); 131 MovePCtoLROffset = (void*)MCE.getCurrentPCValue(); 132 MCE.emitWordBE(0x48000005); // bl 1 133 break; 134 } 135 MCE.processDebugLoc(MI.getDebugLoc(), false); 136 } 137 } 138 139 unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI, 140 unsigned OpNo) const { 141 const MachineOperand &MO = MI.getOperand(OpNo); 142 assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MTCRF8 || 143 MI.getOpcode() == PPC::MFOCRF) && 144 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 145 return 0x80 >> getPPCRegisterNumbering(MO.getReg()); 146 } 147 148 MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO, 149 unsigned RelocID) const { 150 // If in PIC mode, we need to encode the negated address of the 151 // 'movepctolr' into the unrelocated field. After relocation, we'll have 152 // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm 153 // field, we get &gv. This doesn't happen for branch relocations, which are 154 // always implicitly pc relative. 155 intptr_t Cst = 0; 156 if (TM.getRelocationModel() == Reloc::PIC_) { 157 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?"); 158 Cst = -(intptr_t)MovePCtoLROffset - 4; 159 } 160 161 if (MO.isGlobal()) 162 return MachineRelocation::getGV(MCE.getCurrentPCOffset(), RelocID, 163 const_cast<GlobalValue *>(MO.getGlobal()), 164 Cst, isa<Function>(MO.getGlobal())); 165 if (MO.isSymbol()) 166 return MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 167 RelocID, MO.getSymbolName(), Cst); 168 if (MO.isCPI()) 169 return MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 170 RelocID, MO.getIndex(), Cst); 171 172 if (MO.isMBB()) 173 return MachineRelocation::getBB(MCE.getCurrentPCOffset(), 174 RelocID, MO.getMBB()); 175 176 assert(MO.isJTI()); 177 return MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 178 RelocID, MO.getIndex(), Cst); 179 } 180 181 unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI, 182 unsigned OpNo) const { 183 const MachineOperand &MO = MI.getOperand(OpNo); 184 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 185 186 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bx)); 187 return 0; 188 } 189 190 unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI, 191 unsigned OpNo) const { 192 const MachineOperand &MO = MI.getOperand(OpNo); 193 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx)); 194 return 0; 195 } 196 197 unsigned PPCCodeEmitter::getHA16Encoding(const MachineInstr &MI, 198 unsigned OpNo) const { 199 const MachineOperand &MO = MI.getOperand(OpNo); 200 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 201 202 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_high)); 203 return 0; 204 } 205 206 unsigned PPCCodeEmitter::getLO16Encoding(const MachineInstr &MI, 207 unsigned OpNo) const { 208 const MachineOperand &MO = MI.getOperand(OpNo); 209 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 210 211 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low)); 212 return 0; 213 } 214 215 unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI, 216 unsigned OpNo) const { 217 // Encode (imm, reg) as a memri, which has the low 16-bits as the 218 // displacement and the next 5 bits as the register #. 219 assert(MI.getOperand(OpNo+1).isReg()); 220 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16; 221 222 const MachineOperand &MO = MI.getOperand(OpNo); 223 if (MO.isImm()) 224 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits; 225 226 // Add a fixup for the displacement field. 227 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low)); 228 return RegBits; 229 } 230 231 unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI, 232 unsigned OpNo) const { 233 // Encode (imm, reg) as a memrix, which has the low 14-bits as the 234 // displacement and the next 5 bits as the register #. 235 assert(MI.getOperand(OpNo+1).isReg()); 236 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14; 237 238 const MachineOperand &MO = MI.getOperand(OpNo); 239 if (MO.isImm()) 240 return (getMachineOpValue(MI, MO) & 0x3FFF) | RegBits; 241 242 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix)); 243 return RegBits; 244 } 245 246 247 unsigned PPCCodeEmitter::getTLSRegEncoding(const MachineInstr &MI, 248 unsigned OpNo) const { 249 llvm_unreachable("TLS not supported on the old JIT."); 250 return 0; 251 } 252 253 254 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, 255 const MachineOperand &MO) const { 256 257 if (MO.isReg()) { 258 // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 259 // The GPR operand should come through here though. 260 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MTCRF8 && 261 MI.getOpcode() != PPC::MFOCRF) || 262 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 263 return getPPCRegisterNumbering(MO.getReg()); 264 } 265 266 assert(MO.isImm() && 267 "Relocation required in an instruction that we cannot encode!"); 268 return MO.getImm(); 269 } 270 271 #include "PPCGenCodeEmitter.inc" 272
