1 //===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief TargetRegisterInfo interface that is implemented by all hw codegen 12 /// targets. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef AMDGPUREGISTERINFO_H 17 #define AMDGPUREGISTERINFO_H 18 19 #include "llvm/ADT/BitVector.h" 20 #include "llvm/Target/TargetRegisterInfo.h" 21 22 #define GET_REGINFO_HEADER 23 #define GET_REGINFO_ENUM 24 #include "AMDGPUGenRegisterInfo.inc" 25 26 namespace llvm { 27 28 class AMDGPUTargetMachine; 29 class TargetInstrInfo; 30 31 struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo { 32 TargetMachine &TM; 33 const TargetInstrInfo &TII; 34 static const uint16_t CalleeSavedReg; 35 36 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii); 37 38 virtual BitVector getReservedRegs(const MachineFunction &MF) const { 39 assert(!"Unimplemented"); return BitVector(); 40 } 41 42 /// \param RC is an AMDIL reg class. 43 /// 44 /// \returns The ISA reg class that is equivalent to \p RC. 45 virtual const TargetRegisterClass * getISARegClass( 46 const TargetRegisterClass * RC) const { 47 assert(!"Unimplemented"); return NULL; 48 } 49 50 virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const { 51 assert(!"Unimplemented"); return NULL; 52 } 53 54 const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const; 55 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 56 unsigned FIOperandNum, 57 RegScavenger *RS) const; 58 unsigned getFrameRegister(const MachineFunction &MF) const; 59 60 unsigned getIndirectSubReg(unsigned IndirectIndex) const; 61 62 }; 63 64 } // End namespace llvm 65 66 #endif // AMDIDSAREGISTERINFO_H 67
