| /external/clang/test/CodeGenCXX/ |
| debug-info-byval.cpp | 4 class DAG {
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| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 27 const ScheduleDAG *DAG;
31 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {}
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| /external/llvm/include/llvm/CodeGen/ |
| ScoreboardHazardRecognizer.h | 95 const ScheduleDAG *DAG;
108 const ScheduleDAG *DAG,
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| SelectionDAG.h | 1 //===-- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ---------*- C++ -*-===//
118 void checkForCycles(const SelectionDAG *DAG);
121 /// in a low-level Data Dependence DAG representation suitable for instruction
122 /// selection. This DAG is constructed as the first step of instruction
143 /// Root - The root of the entire DAG.
146 /// AllNodes - A linked list of nodes in the current DAG.
178 /// the DAG can optionally implement this interface. This allows the clients
181 /// A DAGUpdateListener automatically registers itself with DAG when it is
185 SelectionDAG &DAG;
188 : Next(D.UpdateListeners), DAG(D)
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 34 /// the DAG and must be handled explicitly by schedulers.
39 SelectionDAG *DAG; // DAG of the current basic block
51 void Run(SelectionDAG *dag, MachineBasicBlock *bb);
82 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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| LegalizeTypes.h | 1 //===-- LegalizeTypes.h - Definition of the DAG Type Legalizer class ------===//
37 SelectionDAG &DAG;
68 return TLI.getTypeAction(*DAG.getContext(), VT);
73 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
119 explicit DAGTypeLegalizer(SelectionDAG &dag)
120 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
127 /// top-down traversal of the dag, legalizing types as it goes. Returns
138 SelectionDAG &getDAG() const { return DAG; }
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| LegalizeDAG.cpp | 53 SelectionDAG &DAG;
64 explicit SelectionDAGLegalize(SelectionDAG &DAG);
159 DAG.RemoveDeadNode(N);
165 DAG.ReplaceAllUsesWith(Old, New);
169 DAG.ReplaceAllUsesWith(Old, New);
173 DAG.ReplaceAllUsesWith(Old, New);
194 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
208 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
211 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
212 : SelectionDAG::DAGUpdateListener(dag),
[all...] |
| LegalizeVectorOps.cpp | 36 SelectionDAG& DAG;
83 VectorLegalizer(SelectionDAG& dag) :
84 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
90 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
91 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) {
113 DAG.AssignTopologicalOrder();
114 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
115 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I
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| SelectionDAGBuilder.h | 1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
83 /// CurDebugLoc - current file + line number. Changes as we build the DAG.
287 SelectionDAG &DAG;
322 /// no subsequent DAG nodes should be created.
328 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
330 : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
331 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
354 /// getRoot - Return the current virtual root of the Selection DAG,
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| TargetLowering.cpp | 47 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
49 const Function *F = DAG.getMachineFunction().getFunction();
70 SDValue TargetLowering::makeLibCall(SelectionDAG &DAG,
80 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
85 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
87 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
89 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
93 Callee, Args, DAG, dl);
102 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
186 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl)
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| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.h | 36 const ScheduleDAGMI *DAG;
78 DAG(0), TII(0), TRI(0), MRI(0) {
94 virtual void initialize(ScheduleDAGMI *dag);
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| SIISelLowering.cpp | 1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
11 /// \brief Custom DAG lowering for SI
85 DebugLoc DL, SelectionDAG &DAG,
90 MachineFunction &MF = DAG.getMachineFunction();
140 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
141 getTargetMachine(), ArgLocs, *DAG.getContext());
170 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
177 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
191 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
197 Regs.push_back(DAG.getUNDEF(VT))
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| R600ISelLowering.cpp | 1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
11 /// \brief Custom DAG lowering for R600
305 // Custom DAG Lowering Operations
311 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
313 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
314 case ISD::ROTL: return LowerROTL(Op, DAG);
315 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
316 case ISD::SELECT: return LowerSELECT(Op, DAG);
317 case ISD::STORE: return LowerSTORE(Op, DAG);
318 case ISD::LOAD: return LowerLOAD(Op, DAG);
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.h | 103 /// Perform platform specific DAG postprocessing.
134 VLIWMachineScheduler *DAG;
156 DAG(0), SchedModel(0), Available(ID, Name+".A"),
167 void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
168 DAG = dag;
191 VLIWMachineScheduler *DAG;
208 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
210 virtual void initialize(ScheduleDAGMI *dag);
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| HexagonISelLowering.cpp | 1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
11 // into a selection DAG.
275 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
287 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
290 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
291 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
305 DebugLoc dl, SelectionDAG &DAG) const {
311 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
312 getTargetMachine(), RVLocs, *DAG.getContext());
324 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag)
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| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
374 SelectionDAG &DAG = CLI.DAG;
403 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
404 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT);
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| MipsISelLowering.cpp | 1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
11 // selection DAG.
73 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
74 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
75 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
78 static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
82 return DAG.getTargetGlobalAddress(N->getGlobal(), Op.getDebugLoc(), Ty, 0,
85 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
87 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
89 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag)
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 1 //===-- MBlazeISelLowering.cpp - MBlaze DAG Lowering Implementation -------===//
11 // selection DAG.
200 SelectionDAG &DAG) const {
203 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
204 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
205 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
206 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
207 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
208 case ISD::VASTART: return LowerVASTART(Op, DAG);
573 SelectionDAG &DAG) const
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| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
187 SelectionDAG &DAG) const {
191 case ISD::SRA: return LowerShifts(Op, DAG);
192 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
193 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
194 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
195 case ISD::SETCC: return LowerSETCC(Op, DAG);
196 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
197 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
198 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
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| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
11 // selection DAG.
84 DebugLoc dl, SelectionDAG &DAG) const {
86 MachineFunction &MF = DAG.getMachineFunction();
92 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
93 DAG.getTarget(), RVLocs, *DAG.getContext());
108 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
113 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
123 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy())
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| /external/llvm/lib/CodeGen/ |
| MachineScheduler.cpp | 65 // DAG subtrees must have at least this many nodes.
180 /// consistent with the DAG builder, which traverses the interior of the
183 /// This design avoids exposing scheduling boundaries to the DAG builder,
184 /// simplifying the DAG builder's support for "special" target instructions.
235 // boundary at the bottom of the region. The DAG does not include RegionEnd,
512 /// only includes instructions that have DAG nodes, not scheduling boundaries.
530 // Initialize the strategy before modifying the DAG.
538 // Initialize ready queues now that the DAG and priority data are finalized.
563 /// Build the DAG and setup three register pressure trackers.
572 // Build the DAG, and compute current register pressure
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 10 // selection DAG.
244 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
247 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
248 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
413 SelectionDAG &DAG = CLI.DAG;
428 Chain = DAG.getCALLSEQ_START(Chain,
429 DAG.getIntPtrConstant(uniqueCallSite, true));
449 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
451 DAG.getConstant(paramCount, MVT::i32)
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| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
163 // We have target-specific dag combine patterns for the following nodes:
171 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
174 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
175 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
176 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
177 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
178 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
179 case ISD::LOAD: return LowerLOAD(Op, DAG);
180 case ISD::STORE: return LowerSTORE(Op, DAG);
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| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===//
11 // selection DAG.
823 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
825 MachineFunction &MF = DAG.getMachineFunction();
842 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
846 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
847 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
851 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
852 DAG.getConstant(8, getPointerTy()));
861 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy())
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| /external/llvm/lib/Transforms/Vectorize/ |
| BBVectorize.cpp | 309 DenseMap<ValuePair, size_t> &DAG,
320 DenseMap<ValuePair, size_t> &DAG, ValuePair J);
748 // the pairing with the largest dag meeting the depth requirement on at
749 // least one branch. Then select all pairings that are part of that dag
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