| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 192 SDValue Op0, Op1;
196 if (!SelectADDRrr(Op, Op0, Op1))
197 SelectADDRri(Op, Op0, Op1);
202 OutOps.push_back(Op1);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 275 MachineOperand Op1 = MI->getOperand(S1);
278 ChangeOpInto(MI->getOperand(S2), Op1);
|
| HexagonISelDAGToDAG.cpp | 789 SDValue OP1;
824 OP1 = Sext1;
835 OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
845 OP0, OP1);
[all...] |
| HexagonHardwareLoops.cpp | 523 const MachineOperand &Op1 = CondI->getOperand(1);
527 if (Op1.isReg()) {
528 if (Op2.isImm() || Op1.getReg() == IVReg)
531 EndValue = &Op1;
[all...] |
| /external/llvm/lib/DebugInfo/ |
| DWARFDebugFrame.cpp | 110 uint64_t Op1 = Opcode & DWARF_CFI_PRIMARY_OPERAND_MASK;
115 addInstruction(Primary, Op1);
118 addInstruction(Primary, Op1, Data.getULEB128(Offset));
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 492 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits
502 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
504 Ops[1].getAsInteger(10, Op1);
508 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
531 uint32_t Op1 = (Bits >> 11) & 0x7;
546 return "s3_" + utostr(Op1) + "_c" + utostr(CRn)
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 288 SDValue Op0, Op1;
292 if (!SelectAddr(Op, Op0, Op1))
298 OutOps.push_back(Op1);
|
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 236 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
248 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
254 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
263 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
342 unsigned Op1, Op2;
343 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
347 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
355 unsigned Op1, Op2;
356 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
360 Inst.addOperand(MCOperand::CreateImm(Op1));
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
32 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
36 if (ConstantInt *CUI = dyn_cast<ConstantInt>(Op1))
44 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) {
48 Op1->getName());
312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,
320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) {
325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this));
336 if (Op1->uge(TypeBits))
[all...] |
| InstCombineMulDivRem.cpp | 100 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
102 if (Value *V = SimplifyMulInst(Op0, Op1, TD))
108 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X
111 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
163 if (isa<Constant>(Op1)) {
175 if (Value *Op1v = dyn_castNegVal(Op1))
181 Value *Op1C = Op1;
187 BO = dyn_cast<BinaryOperator>(Op1);
219 return BinaryOperator::CreateAnd(Op0, Op1);
226 return BinaryOperator::CreateShl(Op1, Y)
[all...] |
| InstCombineAddSub.cpp | [all...] |
| InstCombineCalls.cpp | 600 Value *Op1 = Builder->CreateBitCast(II->getArgOperand(1),
617 Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1,
[all...] |
| InstCombineCasts.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 339 SDValue Op1 = N->getOperand(1);
394 if (SelectDirectAddr(Op1, Addr)) {
427 SelectADDRsi64(Op1.getNode(), Op1, Base, Offset):
428 SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
461 SelectADDRri64(Op1.getNode(), Op1, Base, Offset):
462 SelectADDRri(Op1.getNode(), Op1, Base, Offset))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 580 SDValue Op1 = Op.getOperand(1);
584 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
602 assert(MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits()
619 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
626 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
628 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
659 SDValue Op1 = Op.getOperand(1);
676 assert(VT.getSizeInBits() == Op1.getValueType().getSizeInBits(
[all...] |
| FastISel.cpp | 386 unsigned Op1 = getRegForValue(I->getOperand(1));
387 if (Op1 == 0) return false;
391 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
447 unsigned Op1 = getRegForValue(I->getOperand(1));
448 if (Op1 == 0)
458 Op1, Op1IsKill);
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 160 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS))
161 if (Op1->getOpcode() == OpcodeToExpand) {
163 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1);
198 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS);
201 !Op1 || Op1->getOpcode() != OpcodeToExtract)
206 Value *C = Op1->getOperand(0), *D = Op1->getOperand(1);
269 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)
[all...] |
| ValueTracking.cpp | 46 static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
60 llvm::ComputeMaskedBits(Op1, KnownZero2, KnownOne2, TD, Depth+1);
86 llvm::ComputeMaskedBits(Op1, KnownZero2, KnownOne2, TD, Depth+1);
132 static void ComputeMaskedBitsMul(Value *Op0, Value *Op1, bool NSW,
137 ComputeMaskedBits(Op1, KnownZero, KnownOne, TD, Depth+1);
146 if (Op0 == Op1) {
163 isKnownNonZero(Op1, TD, Depth));
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 405 SDValue Op1 = N->getOperand(1);
410 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO);
417 unsigned Op1Opc = Op1.getOpcode();
427 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
428 Op1.getOperand(0).getOpcode() != ISD::SRL) {
429 std::swap(Op0, Op1);
435 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
436 Op1.getOperand(0).getOpcode() != ISD::SRL) {
437 std::swap(Op0, Op1);
448 isInt32Immediate(Op1.getOperand(1), Value))
[all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | 604 unsigned Op1, Op2, NewDstIdx;
605 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
607 if (Op1 == UseOpIdx)
610 NewDstIdx = Op1;
[all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | 62 const char *SelectInst::areInvalidOperands(Value *Op0, Value *Op1, Value *Op2) {
63 if (Op1->getType() != Op2->getType())
70 VectorType *ET = dyn_cast<VectorType>(Op1->getType());
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 112 unsigned Op1, bool Op1IsKill);
116 unsigned Op1, bool Op1IsKill,
129 unsigned Op1, bool Op1IsKill,
324 unsigned Op1, bool Op1IsKill) {
331 .addReg(Op1, Op1IsKill * RegState::Kill));
335 .addReg(Op1, Op1IsKill * RegState::Kill));
346 unsigned Op1, bool Op1IsKill,
354 .addReg(Op1, Op1IsKill * RegState::Kill)
359 .addReg(Op1, Op1IsKill * RegState::Kill)
415 unsigned Op1, bool Op1IsKill
[all...] |
| ARMLoadStoreOptimizer.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | [all...] |
