| /external/icu4c/test/intltest/ |
| tscoll.h | 26 struct Order
28 int32_t order; member in struct:IntlTestCollator::Order
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
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| ssearch.cpp | 674 struct Order
676 int32_t order; member in struct:Order
689 void add(int32_t order, int32_t low, int32_t high);
690 const Order *get(int32_t index) const;
699 Order *list;
707 list = new Order[listMax];
716 int32_t order, low, high; local
732 list = new Order[listMax];
738 order = ucol_next(elems, &status);
741 if (order != UCOL_NULLORDER)
788 const Order *order = get(index); local
799 const Order *order = get(index); local
810 const Order *order = get(index); local
875 const Order *order = list.get(i); local
893 const Order *order = list.get(i); local
990 int32_t order, low, high; local
1115 uint64_t order; local
[all...] |
| /external/aac/libAACdec/src/ |
| aacdec_tns.h | 99 TNS_MAXIMUM_ORDER = 20, /* 12 for AAC-LC and AAC-SSR. Set to 20 for AAC-Main (AOT 1). Some broken encoders also do order 20 for AAC-LC :( */
113 UCHAR Order;
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| /external/llvm/lib/CodeGen/ |
| AllocationOrder.h | 1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
30 ArrayRef<MCPhysReg> Order;
42 /// Get the allocation order without reordered hints.
43 ArrayRef<MCPhysReg> getOrder() const { return Order; }
45 /// Return the next physical register in the allocation order, or 0.
51 while (Pos < int(Order.size())) {
52 unsigned Reg = Order[Pos++];
60 /// Limit'th register in the RegisterClassInfo allocation order
[all...] |
| TargetRegisterInfo.cpp | 123 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
124 for (unsigned i = 0; i != Order.size(); ++i)
125 R.set(Order[i]);
255 ArrayRef<MCPhysReg> Order,
277 // Check that Phys is in the allocation order. We shouldn't heed hints
278 // from VirtReg's register class if they aren't in the allocation order. The
280 if (std::find(Order.begin(), Order.end(), Phys) == Order.end())
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| CriticalAntiDepBreaker.cpp | 366 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
367 for (unsigned i = 0; i != Order.size(); ++i) {
368 unsigned NewReg = Order[i];
514 // the anti-dependencies in an instruction in order to be effective.
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| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 34 OwningArrayPtr<MCPhysReg> Order;
41 return makeArrayRef(Order.get(), NumRegs);
89 /// getOrder - Returns the preferred allocation order for RC. The order
115 /// Get the minimum register cost in RC's allocation order.
|
| ScheduleDAG.h | 52 Order ///< Any other ordering dependency.
85 /// Order - Additional information about Order dependencies.
126 : Dep(S, Order), Contents(), Latency(0), MinLatency(0) {
138 case Order:
198 /// isNormalMemory - Test if this is an Order dependence between two
202 return getKind() == Order && (Contents.OrdKind == MayAliasMem
206 /// isMustAlias - Test if this is an Order dependence that is marked
210 return getKind() == Order && Contents.OrdKind == MustAliasMem;
218 return getKind() == Order && Contents.OrdKind >= Weak
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 50 unsigned Order;
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
101 // Returns the SDNodeOrder. This is the order of the preceding node in the
103 unsigned getOrder() { return Order; }
|
| SelectionDAGDumper.cpp | 494 if (unsigned Order = G->GetOrdering(this))
495 OS << " [ORD=" << Order << ']';
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| SelectionDAGBuilder.cpp | [all...] |
| /frameworks/opt/vcard/tests/src/com/android/vcard/tests/ |
| VCardParserTests.java | 37 private enum Order {
46 private final List<Order> mHistory = new ArrayList<Order>();
47 private final List<Order> mExpectedOrder = new ArrayList<Order>();
49 public MockVCardInterpreter addExpectedOrder(Order order) {
50 mExpectedOrder.add(order);
54 private void inspectOrder(Order order) {
[all...] |
| /external/eigen/unsupported/Eigen/src/Splines/ |
| Spline.h | 94 * \brief Evaluation of spline derivatives of up-to given order.
100 * for i ranging between 0 and order.
103 * \param order The order up to which the derivatives are computed.
106 derivatives(Scalar u, DenseIndex order) const;
115 derivatives(Scalar u, DenseIndex order = DerivativeOrder) const;
137 * \brief Computes the non-zero spline basis function derivatives up to given order.
143 * with i ranging from 0 up to the specified order.
147 * \param order The order up to which the basis function derivatives are computes
[all...] |
| /external/llvm/lib/MC/ |
| MachObjectWriter.cpp | 426 // when we see the attribute, but that makes getting the order in the symbol
496 // The particular order that we collect the symbols and create the string
568 // External and undefined symbols are required to be in lexicographic order.
589 const SmallVectorImpl<MCSectionData*> &Order = Layout.getSectionOrder();
590 for (int i = 0, n = Order.size(); i != n ; ++i) {
591 const MCSectionData *SD = Order[i];
865 // Write the section relocation entries, in reverse order to match 'as'
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUStructurizeCFG.cpp | 179 RNVector Order;
280 /// \brief Build up the general order of nodes
284 for (Order.clear(); I != E; ++I) {
286 Order.append(Nodes.begin(), Nodes.end());
438 for (RNVector::reverse_iterator OI = Order.rbegin(), OE = Order.rend();
642 BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() :
643 Order.back()->getEntry();
676 if (Order.empty() && ExitUseAllowed) {
726 /// Take one node from the order vector and wire it u
[all...] |
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 750 // The list of overlaps doesn't need to have any particular order, and Reg
847 ArrayRef<Record*> Order = RC.getOrder();
856 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
857 Record *Reg = Order[i];
866 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
867 Record *Reg = Order[i];
[all...] |
| CodeGenRegisters.cpp | 188 // Merge two RegUnitLists maintaining the order and removing duplicates.
239 // Here the order is important - earlier subregs take precedence.
281 // Work backwards in the Indices vector in order to compose subregs bottom-up.
491 // Also compute the TopoSigId in post-order.
721 // Allocation order 0 is the full set. AltOrders provides others.
726 // Default allocation order always contains all registers.
735 SetTheory::RecSet Order;
737 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
738 Orders[1 + i].append(Order.begin(), Order.end())
[all...] |
| /external/clang/lib/CodeGen/ |
| CGAtomic.cpp | 186 uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) {
205 CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order);
218 Load->setAtomic(Order);
233 Store->setAtomic(Order);
296 CGF.Builder.CreateAtomicRMW(Op, Ptr, LoadVal1, Order);
334 llvm::Value *Ptr, *Order, *OrderFail = 0, *Val1 = 0, *Val2 = 0;
344 Order = EmitScalarExpr(E->getOrder());
455 Args.add(RValue::get(Order),
457 Order = OrderFail;
460 // int order)
[all...] |
| CGBuiltin.cpp | 792 // doesn't implicitly ignore high-order bits when doing
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 175 /// defined. If the instructions are out of order, try to reorder them.
[all...] |
