| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 250 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
251 OutMI.setOpcode(NewOpc);
255 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
256 OutMI.setOpcode(NewOpc);
426 unsigned NewOpc;
429 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
430 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
431 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
432 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
433 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 439 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
440 MI.setDesc(TII.get(NewOpc));
473 unsigned NewOpc = Opcode;
483 NewOpc = immediateOffsetOpcode(Opcode);
495 NewOpc = negativeOffsetOpcode(Opcode);
500 NewOpc = positiveOffsetOpcode(Opcode);
521 if (NewOpc != Opcode)
522 MI.setDesc(TII.get(NewOpc));
555 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
|
| ARMLoadStoreOptimizer.cpp | 776 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
875 unsigned NewOpc = 0;
893 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);
912 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);
930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
939 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| Thumb1RegisterInfo.cpp | 462 unsigned NewOpc = convertToNonSPOpcode(Opcode);
463 if (NewOpc != Opcode && FrameReg != ARM::SP)
464 MI.setDesc(TII.get(NewOpc));
|
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsLongBranch.cpp | 220 unsigned NewOpc = TII->GetOppositeBranchOpc(Br->getOpcode());
221 const MCInstrDesc &NewDesc = TII->get(NewOpc);
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | [all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 353 unsigned NewOpc = N->getOpcode();
363 NewOpc = ISD::FP_TO_SINT;
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
[all...] |
