| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 108 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
119 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
121 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
122 return scavengeRegister(RegClass, MBBI, SPAdj);
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| RegisterClassInfo.h | 46 OwningArrayPtr<RCInfo> RegClass;
70 const RCInfo &RCI = RegClass[RC->getID()];
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| MachineRegisterInfo.h | 329 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 79 unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
80 return (AMDGPU::SSrc_32RegClassID == RegClass) ||
81 (AMDGPU::SSrc_64RegClassID == RegClass) ||
82 (AMDGPU::VSrc_32RegClassID == RegClass) ||
83 (AMDGPU::VSrc_64RegClassID == RegClass);
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| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 417 /// \brief Test if RegClass is one of the VSrc classes
418 static bool isVSrc(unsigned RegClass) {
419 return AMDGPU::VSrc_32RegClassID == RegClass ||
420 AMDGPU::VSrc_64RegClassID == RegClass;
423 /// \brief Test if RegClass is one of the SSrc classes
424 static bool isSSrc(unsigned RegClass) {
425 return AMDGPU::SSrc_32RegClassID == RegClass ||
426 AMDGPU::SSrc_64RegClassID == RegClass;
493 /// \brief Does "Op" fit into register class "RegClass" ?
495 unsigned RegClass) const
[all...] |
| SIISelLowering.h | 35 bool fitsRegClass(SelectionDAG &DAG, SDValue &Op, unsigned RegClass) const;
37 unsigned RegClass, bool &ScalarSlotUsed) const;
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| R600InstrInfo.cpp | 301 switch (MI->getDesc().OpInfo->RegClass) {
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| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 45 const TargetRegisterClass &RegClass,
51 if (RegClass.contains(*AR)) {
63 const TargetRegisterClass &RegClass,
65 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x';
77 if (RegClass.contains(*AR)) {
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| AArch64FrameLowering.h | 31 const TargetRegisterClass *RegClass; // E.g. GPR64RegClass
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| AArch64FrameLowering.cpp | 450 if (PossClasses[ClassIdx].RegClass->contains(Reg))
455 const TargetRegisterClass &TheClass = *PossClasses[ClassIdx].RegClass;
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| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
76 RCInfo &RCI = RegClass[RC->getID()];
112 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
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| MachineRegisterInfo.cpp | 93 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
94 assert(RegClass && "Cannot create register without RegClass!");
95 assert(RegClass->isAllocatable() &&
96 "Virtual register RegClass must be allocatable.");
101 VRegInfo[Reg].first = RegClass;
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| TargetInstrInfo.cpp | 45 short RegClass = MCID.OpInfo[OpNum].RegClass;
47 return TRI->getPointerRegClass(MF, RegClass);
50 if (RegClass < 0)
54 return TRI->getRegClass(RegClass);
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| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 59 /// RegClass - This specifies the register class enumeration of the operand
63 int16_t RegClass;
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| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 152 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
721 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
726 return getReg(RegClass, RegNum);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 278 unsigned &RegClass, unsigned &Cost,
291 RegClass = RC->getID();
300 RegClass = RC->getID();
308 RegClass = RC->getID();
313 RegClass = TLI->getRepRegClassFor(VT)->getID();
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 739 // Verify that all altorder members are regclass members.
[all...] |
| CodeGenDAGPatterns.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 626 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
[all...] |
