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Searched
refs:RegUnit
(Results
1 - 9
of
9
) sorted by null
/external/llvm/include/llvm/CodeGen/
LiveRegMatrix.h
19
// the virtual register is inserted into the LiveIntervalUnion for each
regunit
130
/// Check for
regunit
interference only.
139
LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned
RegUnit
);
141
/// Directly access the live interval unions per
regunit
.
142
/// This returns an array indexed by the
regunit
number.
MachineRegisterInfo.h
382
void setRegUnitUsed(unsigned
RegUnit
) {
383
UsedRegUnits.set(
RegUnit
);
/external/llvm/lib/CodeGen/
LiveRegMatrix.cpp
129
unsigned
RegUnit
) {
130
LiveIntervalUnion::Query &Q = Queries[
RegUnit
];
131
Q.init(UserTag, &VirtReg, &Matrix[
RegUnit
]);
MachineTraceMetrics.cpp
588
// Associate each
regunit
with an instruction operand. Depending on the
590
//
regunit
, or the highest operand to read the
regunit
.
593
unsigned
RegUnit
;
598
unsigned getSparseSetIndex() const { return
RegUnit
; }
600
LiveRegUnit(unsigned RU) :
RegUnit
(RU), Cycle(0), MI(0), Op(0) {}
604
// Identify physreg dependencies for UseMI, and update the live
regunit
803
// This
regunit
is dead above MI.
[
all
...]
/external/llvm/include/llvm/MC/
MCRegisterInfo.h
159
const uint16_t (*RegUnitRoots)[2]; // Pointer to
regunit
root table.
180
/// differentially encoded register and
regunit
lists in DiffLists.
516
MCRegUnitRootIterator(unsigned
RegUnit
, const MCRegisterInfo *MCRI) {
517
assert(
RegUnit
< MCRI->getNumRegUnits() && "Invalid register unit");
518
Reg0 = MCRI->RegUnitRoots[
RegUnit
][0];
519
Reg1 = MCRI->RegUnitRoots[
RegUnit
][1];
/external/llvm/include/llvm/Target/
TargetRegisterInfo.h
383
/// hasRegUnit - Returns true if Reg contains
RegUnit
.
384
bool hasRegUnit(unsigned Reg, unsigned
RegUnit
) const {
386
if (*Units ==
RegUnit
)
588
virtual unsigned getRegUnitWeight(unsigned
RegUnit
) const = 0;
607
virtual const int *getRegUnitPressureSets(unsigned
RegUnit
) const = 0;
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...]
/external/llvm/utils/TableGen/
CodeGenRegisters.h
395
struct
RegUnit
{
396
// Weight assigned to this
RegUnit
for estimating register pressure.
401
// Each native
RegUnit
corresponds to one or two root registers. The full
410
RegUnit
() : Weight(0), RegClassUnitSetsIdx(0) { Roots[0] = Roots[1] = 0; }
454
SmallVector<
RegUnit
, 8> RegUnits;
468
// class's units and any inferred
RegUnit
supersets.
587
RegUnit
&getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
588
const
RegUnit
&getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
RegisterInfoEmitter.cpp
198
<< "getRegUnitWeight(unsigned
RegUnit
) const {\n"
199
<< " assert(
RegUnit
< " << RegBank.getNumNativeRegUnits()
205
const
RegUnit
&RU = RegBank.getRegUnit(UnitIdx);
206
assert(RU.Weight < 256 && "
RegUnit
too heavy");
210
<< " return RUWeightTable[
RegUnit
];\n";
295
<< "getRegUnitPressureSets(unsigned
RegUnit
) const {\n"
296
<< " assert(
RegUnit
< " << RegBank.getNumNativeRegUnits()
304
<< " unsigned SetListStart = RUSetStartTable[
RegUnit
];\n"
554
// Differentially encoded register and
regunit
lists allow for better
825
// Emit the table of register unit roots. Each
regunit
has one or two roo
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all
...]
CodeGenRegisters.cpp
377
// Create a
RegUnit
representing this alias edge, and add it to both
561
const
RegUnit
&RU = RegBank.getRegUnit(RegUnits[rui]);
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all
...]
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