1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // These classes wrap the information about a call or function 11 // definition used to handle ABI compliancy. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "TargetInfo.h" 16 #include "ABIInfo.h" 17 #include "CodeGenFunction.h" 18 #include "clang/AST/RecordLayout.h" 19 #include "clang/Frontend/CodeGenOptions.h" 20 #include "llvm/ADT/Triple.h" 21 #include "llvm/IR/DataLayout.h" 22 #include "llvm/IR/Type.h" 23 #include "llvm/Support/raw_ostream.h" 24 using namespace clang; 25 using namespace CodeGen; 26 27 static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder, 28 llvm::Value *Array, 29 llvm::Value *Value, 30 unsigned FirstIndex, 31 unsigned LastIndex) { 32 // Alternatively, we could emit this as a loop in the source. 33 for (unsigned I = FirstIndex; I <= LastIndex; ++I) { 34 llvm::Value *Cell = Builder.CreateConstInBoundsGEP1_32(Array, I); 35 Builder.CreateStore(Value, Cell); 36 } 37 } 38 39 static bool isAggregateTypeForABI(QualType T) { 40 return !CodeGenFunction::hasScalarEvaluationKind(T) || 41 T->isMemberFunctionPointerType(); 42 } 43 44 ABIInfo::~ABIInfo() {} 45 46 ASTContext &ABIInfo::getContext() const { 47 return CGT.getContext(); 48 } 49 50 llvm::LLVMContext &ABIInfo::getVMContext() const { 51 return CGT.getLLVMContext(); 52 } 53 54 const llvm::DataLayout &ABIInfo::getDataLayout() const { 55 return CGT.getDataLayout(); 56 } 57 58 59 void ABIArgInfo::dump() const { 60 raw_ostream &OS = llvm::errs(); 61 OS << "(ABIArgInfo Kind="; 62 switch (TheKind) { 63 case Direct: 64 OS << "Direct Type="; 65 if (llvm::Type *Ty = getCoerceToType()) 66 Ty->print(OS); 67 else 68 OS << "null"; 69 break; 70 case Extend: 71 OS << "Extend"; 72 break; 73 case Ignore: 74 OS << "Ignore"; 75 break; 76 case Indirect: 77 OS << "Indirect Align=" << getIndirectAlign() 78 << " ByVal=" << getIndirectByVal() 79 << " Realign=" << getIndirectRealign(); 80 break; 81 case Expand: 82 OS << "Expand"; 83 break; 84 } 85 OS << ")\n"; 86 } 87 88 TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; } 89 90 // If someone can figure out a general rule for this, that would be great. 91 // It's probably just doomed to be platform-dependent, though. 92 unsigned TargetCodeGenInfo::getSizeOfUnwindException() const { 93 // Verified for: 94 // x86-64 FreeBSD, Linux, Darwin 95 // x86-32 FreeBSD, Linux, Darwin 96 // PowerPC Linux, Darwin 97 // ARM Darwin (*not* EABI) 98 // AArch64 Linux 99 return 32; 100 } 101 102 bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args, 103 const FunctionNoProtoType *fnType) const { 104 // The following conventions are known to require this to be false: 105 // x86_stdcall 106 // MIPS 107 // For everything else, we just prefer false unless we opt out. 108 return false; 109 } 110 111 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays); 112 113 /// isEmptyField - Return true iff a the field is "empty", that is it 114 /// is an unnamed bit-field or an (array of) empty record(s). 115 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD, 116 bool AllowArrays) { 117 if (FD->isUnnamedBitfield()) 118 return true; 119 120 QualType FT = FD->getType(); 121 122 // Constant arrays of empty records count as empty, strip them off. 123 // Constant arrays of zero length always count as empty. 124 if (AllowArrays) 125 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { 126 if (AT->getSize() == 0) 127 return true; 128 FT = AT->getElementType(); 129 } 130 131 const RecordType *RT = FT->getAs<RecordType>(); 132 if (!RT) 133 return false; 134 135 // C++ record fields are never empty, at least in the Itanium ABI. 136 // 137 // FIXME: We should use a predicate for whether this behavior is true in the 138 // current ABI. 139 if (isa<CXXRecordDecl>(RT->getDecl())) 140 return false; 141 142 return isEmptyRecord(Context, FT, AllowArrays); 143 } 144 145 /// isEmptyRecord - Return true iff a structure contains only empty 146 /// fields. Note that a structure with a flexible array member is not 147 /// considered empty. 148 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) { 149 const RecordType *RT = T->getAs<RecordType>(); 150 if (!RT) 151 return 0; 152 const RecordDecl *RD = RT->getDecl(); 153 if (RD->hasFlexibleArrayMember()) 154 return false; 155 156 // If this is a C++ record, check the bases first. 157 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 158 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 159 e = CXXRD->bases_end(); i != e; ++i) 160 if (!isEmptyRecord(Context, i->getType(), true)) 161 return false; 162 163 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 164 i != e; ++i) 165 if (!isEmptyField(Context, *i, AllowArrays)) 166 return false; 167 return true; 168 } 169 170 /// hasNonTrivialDestructorOrCopyConstructor - Determine if a type has either 171 /// a non-trivial destructor or a non-trivial copy constructor. 172 static bool hasNonTrivialDestructorOrCopyConstructor(const RecordType *RT) { 173 const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl()); 174 if (!RD) 175 return false; 176 177 return !RD->hasTrivialDestructor() || RD->hasNonTrivialCopyConstructor(); 178 } 179 180 /// isRecordWithNonTrivialDestructorOrCopyConstructor - Determine if a type is 181 /// a record type with either a non-trivial destructor or a non-trivial copy 182 /// constructor. 183 static bool isRecordWithNonTrivialDestructorOrCopyConstructor(QualType T) { 184 const RecordType *RT = T->getAs<RecordType>(); 185 if (!RT) 186 return false; 187 188 return hasNonTrivialDestructorOrCopyConstructor(RT); 189 } 190 191 /// isSingleElementStruct - Determine if a structure is a "single 192 /// element struct", i.e. it has exactly one non-empty field or 193 /// exactly one field which is itself a single element 194 /// struct. Structures with flexible array members are never 195 /// considered single element structs. 196 /// 197 /// \return The field declaration for the single non-empty field, if 198 /// it exists. 199 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) { 200 const RecordType *RT = T->getAsStructureType(); 201 if (!RT) 202 return 0; 203 204 const RecordDecl *RD = RT->getDecl(); 205 if (RD->hasFlexibleArrayMember()) 206 return 0; 207 208 const Type *Found = 0; 209 210 // If this is a C++ record, check the bases first. 211 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 212 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 213 e = CXXRD->bases_end(); i != e; ++i) { 214 // Ignore empty records. 215 if (isEmptyRecord(Context, i->getType(), true)) 216 continue; 217 218 // If we already found an element then this isn't a single-element struct. 219 if (Found) 220 return 0; 221 222 // If this is non-empty and not a single element struct, the composite 223 // cannot be a single element struct. 224 Found = isSingleElementStruct(i->getType(), Context); 225 if (!Found) 226 return 0; 227 } 228 } 229 230 // Check for single element. 231 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 232 i != e; ++i) { 233 const FieldDecl *FD = *i; 234 QualType FT = FD->getType(); 235 236 // Ignore empty fields. 237 if (isEmptyField(Context, FD, true)) 238 continue; 239 240 // If we already found an element then this isn't a single-element 241 // struct. 242 if (Found) 243 return 0; 244 245 // Treat single element arrays as the element. 246 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { 247 if (AT->getSize().getZExtValue() != 1) 248 break; 249 FT = AT->getElementType(); 250 } 251 252 if (!isAggregateTypeForABI(FT)) { 253 Found = FT.getTypePtr(); 254 } else { 255 Found = isSingleElementStruct(FT, Context); 256 if (!Found) 257 return 0; 258 } 259 } 260 261 // We don't consider a struct a single-element struct if it has 262 // padding beyond the element type. 263 if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T)) 264 return 0; 265 266 return Found; 267 } 268 269 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) { 270 // Treat complex types as the element type. 271 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) 272 Ty = CTy->getElementType(); 273 274 // Check for a type which we know has a simple scalar argument-passing 275 // convention without any padding. (We're specifically looking for 32 276 // and 64-bit integer and integer-equivalents, float, and double.) 277 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() && 278 !Ty->isEnumeralType() && !Ty->isBlockPointerType()) 279 return false; 280 281 uint64_t Size = Context.getTypeSize(Ty); 282 return Size == 32 || Size == 64; 283 } 284 285 /// canExpandIndirectArgument - Test whether an argument type which is to be 286 /// passed indirectly (on the stack) would have the equivalent layout if it was 287 /// expanded into separate arguments. If so, we prefer to do the latter to avoid 288 /// inhibiting optimizations. 289 /// 290 // FIXME: This predicate is missing many cases, currently it just follows 291 // llvm-gcc (checks that all fields are 32-bit or 64-bit primitive types). We 292 // should probably make this smarter, or better yet make the LLVM backend 293 // capable of handling it. 294 static bool canExpandIndirectArgument(QualType Ty, ASTContext &Context) { 295 // We can only expand structure types. 296 const RecordType *RT = Ty->getAs<RecordType>(); 297 if (!RT) 298 return false; 299 300 // We can only expand (C) structures. 301 // 302 // FIXME: This needs to be generalized to handle classes as well. 303 const RecordDecl *RD = RT->getDecl(); 304 if (!RD->isStruct() || isa<CXXRecordDecl>(RD)) 305 return false; 306 307 uint64_t Size = 0; 308 309 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 310 i != e; ++i) { 311 const FieldDecl *FD = *i; 312 313 if (!is32Or64BitBasicType(FD->getType(), Context)) 314 return false; 315 316 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know 317 // how to expand them yet, and the predicate for telling if a bitfield still 318 // counts as "basic" is more complicated than what we were doing previously. 319 if (FD->isBitField()) 320 return false; 321 322 Size += Context.getTypeSize(FD->getType()); 323 } 324 325 // Make sure there are not any holes in the struct. 326 if (Size != Context.getTypeSize(Ty)) 327 return false; 328 329 return true; 330 } 331 332 namespace { 333 /// DefaultABIInfo - The default implementation for ABI specific 334 /// details. This implementation provides information which results in 335 /// self-consistent and sensible LLVM IR generation, but does not 336 /// conform to any particular ABI. 337 class DefaultABIInfo : public ABIInfo { 338 public: 339 DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 340 341 ABIArgInfo classifyReturnType(QualType RetTy) const; 342 ABIArgInfo classifyArgumentType(QualType RetTy) const; 343 344 virtual void computeInfo(CGFunctionInfo &FI) const { 345 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 346 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 347 it != ie; ++it) 348 it->info = classifyArgumentType(it->type); 349 } 350 351 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 352 CodeGenFunction &CGF) const; 353 }; 354 355 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo { 356 public: 357 DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 358 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 359 }; 360 361 llvm::Value *DefaultABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 362 CodeGenFunction &CGF) const { 363 return 0; 364 } 365 366 ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const { 367 if (isAggregateTypeForABI(Ty)) { 368 // Records with non trivial destructors/constructors should not be passed 369 // by value. 370 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 371 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 372 373 return ABIArgInfo::getIndirect(0); 374 } 375 376 // Treat an enum type as its underlying type. 377 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 378 Ty = EnumTy->getDecl()->getIntegerType(); 379 380 return (Ty->isPromotableIntegerType() ? 381 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 382 } 383 384 ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const { 385 if (RetTy->isVoidType()) 386 return ABIArgInfo::getIgnore(); 387 388 if (isAggregateTypeForABI(RetTy)) 389 return ABIArgInfo::getIndirect(0); 390 391 // Treat an enum type as its underlying type. 392 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 393 RetTy = EnumTy->getDecl()->getIntegerType(); 394 395 return (RetTy->isPromotableIntegerType() ? 396 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 397 } 398 399 //===----------------------------------------------------------------------===// 400 // le32/PNaCl bitcode ABI Implementation 401 //===----------------------------------------------------------------------===// 402 403 class PNaClABIInfo : public ABIInfo { 404 public: 405 PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 406 407 ABIArgInfo classifyReturnType(QualType RetTy) const; 408 ABIArgInfo classifyArgumentType(QualType RetTy, unsigned &FreeRegs) const; 409 410 virtual void computeInfo(CGFunctionInfo &FI) const; 411 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 412 CodeGenFunction &CGF) const; 413 }; 414 415 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo { 416 public: 417 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 418 : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {} 419 }; 420 421 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const { 422 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 423 424 unsigned FreeRegs = FI.getHasRegParm() ? FI.getRegParm() : 0; 425 426 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 427 it != ie; ++it) 428 it->info = classifyArgumentType(it->type, FreeRegs); 429 } 430 431 llvm::Value *PNaClABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 432 CodeGenFunction &CGF) const { 433 return 0; 434 } 435 436 ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty, 437 unsigned &FreeRegs) const { 438 if (isAggregateTypeForABI(Ty)) { 439 // Records with non trivial destructors/constructors should not be passed 440 // by value. 441 FreeRegs = 0; 442 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 443 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 444 445 return ABIArgInfo::getIndirect(0); 446 } 447 448 // Treat an enum type as its underlying type. 449 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 450 Ty = EnumTy->getDecl()->getIntegerType(); 451 452 ABIArgInfo BaseInfo = (Ty->isPromotableIntegerType() ? 453 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 454 455 // Regparm regs hold 32 bits. 456 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32; 457 if (SizeInRegs == 0) return BaseInfo; 458 if (SizeInRegs > FreeRegs) { 459 FreeRegs = 0; 460 return BaseInfo; 461 } 462 FreeRegs -= SizeInRegs; 463 return BaseInfo.isDirect() ? 464 ABIArgInfo::getDirectInReg(BaseInfo.getCoerceToType()) : 465 ABIArgInfo::getExtendInReg(BaseInfo.getCoerceToType()); 466 } 467 468 ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const { 469 if (RetTy->isVoidType()) 470 return ABIArgInfo::getIgnore(); 471 472 if (isAggregateTypeForABI(RetTy)) 473 return ABIArgInfo::getIndirect(0); 474 475 // Treat an enum type as its underlying type. 476 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 477 RetTy = EnumTy->getDecl()->getIntegerType(); 478 479 return (RetTy->isPromotableIntegerType() ? 480 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 481 } 482 483 /// UseX86_MMXType - Return true if this is an MMX type that should use the 484 /// special x86_mmx type. 485 bool UseX86_MMXType(llvm::Type *IRType) { 486 // If the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>, use the 487 // special x86_mmx type. 488 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 && 489 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() && 490 IRType->getScalarSizeInBits() != 64; 491 } 492 493 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 494 StringRef Constraint, 495 llvm::Type* Ty) { 496 if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) 497 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext()); 498 return Ty; 499 } 500 501 //===----------------------------------------------------------------------===// 502 // X86-32 ABI Implementation 503 //===----------------------------------------------------------------------===// 504 505 /// X86_32ABIInfo - The X86-32 ABI information. 506 class X86_32ABIInfo : public ABIInfo { 507 enum Class { 508 Integer, 509 Float 510 }; 511 512 static const unsigned MinABIStackAlignInBytes = 4; 513 514 bool IsDarwinVectorABI; 515 bool IsSmallStructInRegABI; 516 bool IsMMXDisabled; 517 bool IsWin32FloatStructABI; 518 unsigned DefaultNumRegisterParameters; 519 520 static bool isRegisterSize(unsigned Size) { 521 return (Size == 8 || Size == 16 || Size == 32 || Size == 64); 522 } 523 524 static bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context, 525 unsigned callingConvention); 526 527 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 528 /// such that the argument will be passed in memory. 529 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, 530 unsigned &FreeRegs) const; 531 532 /// \brief Return the alignment to use for the given type on the stack. 533 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const; 534 535 Class classify(QualType Ty) const; 536 ABIArgInfo classifyReturnType(QualType RetTy, 537 unsigned callingConvention) const; 538 ABIArgInfo classifyArgumentType(QualType RetTy, unsigned &FreeRegs, 539 bool IsFastCall) const; 540 bool shouldUseInReg(QualType Ty, unsigned &FreeRegs, 541 bool IsFastCall, bool &NeedsPadding) const; 542 543 public: 544 545 virtual void computeInfo(CGFunctionInfo &FI) const; 546 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 547 CodeGenFunction &CGF) const; 548 549 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool m, bool w, 550 unsigned r) 551 : ABIInfo(CGT), IsDarwinVectorABI(d), IsSmallStructInRegABI(p), 552 IsMMXDisabled(m), IsWin32FloatStructABI(w), 553 DefaultNumRegisterParameters(r) {} 554 }; 555 556 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo { 557 public: 558 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, 559 bool d, bool p, bool m, bool w, unsigned r) 560 :TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, m, w, r)) {} 561 562 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 563 CodeGen::CodeGenModule &CGM) const; 564 565 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 566 // Darwin uses different dwarf register numbers for EH. 567 if (CGM.isTargetDarwin()) return 5; 568 569 return 4; 570 } 571 572 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 573 llvm::Value *Address) const; 574 575 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 576 StringRef Constraint, 577 llvm::Type* Ty) const { 578 return X86AdjustInlineAsmType(CGF, Constraint, Ty); 579 } 580 581 }; 582 583 } 584 585 /// shouldReturnTypeInRegister - Determine if the given type should be 586 /// passed in a register (for the Darwin ABI). 587 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty, 588 ASTContext &Context, 589 unsigned callingConvention) { 590 uint64_t Size = Context.getTypeSize(Ty); 591 592 // Type must be register sized. 593 if (!isRegisterSize(Size)) 594 return false; 595 596 if (Ty->isVectorType()) { 597 // 64- and 128- bit vectors inside structures are not returned in 598 // registers. 599 if (Size == 64 || Size == 128) 600 return false; 601 602 return true; 603 } 604 605 // If this is a builtin, pointer, enum, complex type, member pointer, or 606 // member function pointer it is ok. 607 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() || 608 Ty->isAnyComplexType() || Ty->isEnumeralType() || 609 Ty->isBlockPointerType() || Ty->isMemberPointerType()) 610 return true; 611 612 // Arrays are treated like records. 613 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) 614 return shouldReturnTypeInRegister(AT->getElementType(), Context, 615 callingConvention); 616 617 // Otherwise, it must be a record type. 618 const RecordType *RT = Ty->getAs<RecordType>(); 619 if (!RT) return false; 620 621 // FIXME: Traverse bases here too. 622 623 // For thiscall conventions, structures will never be returned in 624 // a register. This is for compatibility with the MSVC ABI 625 if (callingConvention == llvm::CallingConv::X86_ThisCall && 626 RT->isStructureType()) { 627 return false; 628 } 629 630 // Structure types are passed in register if all fields would be 631 // passed in a register. 632 for (RecordDecl::field_iterator i = RT->getDecl()->field_begin(), 633 e = RT->getDecl()->field_end(); i != e; ++i) { 634 const FieldDecl *FD = *i; 635 636 // Empty fields are ignored. 637 if (isEmptyField(Context, FD, true)) 638 continue; 639 640 // Check fields recursively. 641 if (!shouldReturnTypeInRegister(FD->getType(), Context, 642 callingConvention)) 643 return false; 644 } 645 return true; 646 } 647 648 ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy, 649 unsigned callingConvention) const { 650 if (RetTy->isVoidType()) 651 return ABIArgInfo::getIgnore(); 652 653 if (const VectorType *VT = RetTy->getAs<VectorType>()) { 654 // On Darwin, some vectors are returned in registers. 655 if (IsDarwinVectorABI) { 656 uint64_t Size = getContext().getTypeSize(RetTy); 657 658 // 128-bit vectors are a special case; they are returned in 659 // registers and we need to make sure to pick a type the LLVM 660 // backend will like. 661 if (Size == 128) 662 return ABIArgInfo::getDirect(llvm::VectorType::get( 663 llvm::Type::getInt64Ty(getVMContext()), 2)); 664 665 // Always return in register if it fits in a general purpose 666 // register, or if it is 64 bits and has a single element. 667 if ((Size == 8 || Size == 16 || Size == 32) || 668 (Size == 64 && VT->getNumElements() == 1)) 669 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 670 Size)); 671 672 return ABIArgInfo::getIndirect(0); 673 } 674 675 return ABIArgInfo::getDirect(); 676 } 677 678 if (isAggregateTypeForABI(RetTy)) { 679 if (const RecordType *RT = RetTy->getAs<RecordType>()) { 680 // Structures with either a non-trivial destructor or a non-trivial 681 // copy constructor are always indirect. 682 if (hasNonTrivialDestructorOrCopyConstructor(RT)) 683 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 684 685 // Structures with flexible arrays are always indirect. 686 if (RT->getDecl()->hasFlexibleArrayMember()) 687 return ABIArgInfo::getIndirect(0); 688 } 689 690 // If specified, structs and unions are always indirect. 691 if (!IsSmallStructInRegABI && !RetTy->isAnyComplexType()) 692 return ABIArgInfo::getIndirect(0); 693 694 // Small structures which are register sized are generally returned 695 // in a register. 696 if (X86_32ABIInfo::shouldReturnTypeInRegister(RetTy, getContext(), 697 callingConvention)) { 698 uint64_t Size = getContext().getTypeSize(RetTy); 699 700 // As a special-case, if the struct is a "single-element" struct, and 701 // the field is of type "float" or "double", return it in a 702 // floating-point register. (MSVC does not apply this special case.) 703 // We apply a similar transformation for pointer types to improve the 704 // quality of the generated IR. 705 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext())) 706 if ((!IsWin32FloatStructABI && SeltTy->isRealFloatingType()) 707 || SeltTy->hasPointerRepresentation()) 708 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); 709 710 // FIXME: We should be able to narrow this integer in cases with dead 711 // padding. 712 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size)); 713 } 714 715 return ABIArgInfo::getIndirect(0); 716 } 717 718 // Treat an enum type as its underlying type. 719 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 720 RetTy = EnumTy->getDecl()->getIntegerType(); 721 722 return (RetTy->isPromotableIntegerType() ? 723 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 724 } 725 726 static bool isSSEVectorType(ASTContext &Context, QualType Ty) { 727 return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128; 728 } 729 730 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) { 731 const RecordType *RT = Ty->getAs<RecordType>(); 732 if (!RT) 733 return 0; 734 const RecordDecl *RD = RT->getDecl(); 735 736 // If this is a C++ record, check the bases first. 737 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 738 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 739 e = CXXRD->bases_end(); i != e; ++i) 740 if (!isRecordWithSSEVectorType(Context, i->getType())) 741 return false; 742 743 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 744 i != e; ++i) { 745 QualType FT = i->getType(); 746 747 if (isSSEVectorType(Context, FT)) 748 return true; 749 750 if (isRecordWithSSEVectorType(Context, FT)) 751 return true; 752 } 753 754 return false; 755 } 756 757 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty, 758 unsigned Align) const { 759 // Otherwise, if the alignment is less than or equal to the minimum ABI 760 // alignment, just use the default; the backend will handle this. 761 if (Align <= MinABIStackAlignInBytes) 762 return 0; // Use default alignment. 763 764 // On non-Darwin, the stack type alignment is always 4. 765 if (!IsDarwinVectorABI) { 766 // Set explicit alignment, since we may need to realign the top. 767 return MinABIStackAlignInBytes; 768 } 769 770 // Otherwise, if the type contains an SSE vector type, the alignment is 16. 771 if (Align >= 16 && (isSSEVectorType(getContext(), Ty) || 772 isRecordWithSSEVectorType(getContext(), Ty))) 773 return 16; 774 775 return MinABIStackAlignInBytes; 776 } 777 778 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal, 779 unsigned &FreeRegs) const { 780 if (!ByVal) { 781 if (FreeRegs) { 782 --FreeRegs; // Non byval indirects just use one pointer. 783 return ABIArgInfo::getIndirectInReg(0, false); 784 } 785 return ABIArgInfo::getIndirect(0, false); 786 } 787 788 // Compute the byval alignment. 789 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8; 790 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign); 791 if (StackAlign == 0) 792 return ABIArgInfo::getIndirect(4); 793 794 // If the stack alignment is less than the type alignment, realign the 795 // argument. 796 if (StackAlign < TypeAlign) 797 return ABIArgInfo::getIndirect(StackAlign, /*ByVal=*/true, 798 /*Realign=*/true); 799 800 return ABIArgInfo::getIndirect(StackAlign); 801 } 802 803 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const { 804 const Type *T = isSingleElementStruct(Ty, getContext()); 805 if (!T) 806 T = Ty.getTypePtr(); 807 808 if (const BuiltinType *BT = T->getAs<BuiltinType>()) { 809 BuiltinType::Kind K = BT->getKind(); 810 if (K == BuiltinType::Float || K == BuiltinType::Double) 811 return Float; 812 } 813 return Integer; 814 } 815 816 bool X86_32ABIInfo::shouldUseInReg(QualType Ty, unsigned &FreeRegs, 817 bool IsFastCall, bool &NeedsPadding) const { 818 NeedsPadding = false; 819 Class C = classify(Ty); 820 if (C == Float) 821 return false; 822 823 unsigned Size = getContext().getTypeSize(Ty); 824 unsigned SizeInRegs = (Size + 31) / 32; 825 826 if (SizeInRegs == 0) 827 return false; 828 829 if (SizeInRegs > FreeRegs) { 830 FreeRegs = 0; 831 return false; 832 } 833 834 FreeRegs -= SizeInRegs; 835 836 if (IsFastCall) { 837 if (Size > 32) 838 return false; 839 840 if (Ty->isIntegralOrEnumerationType()) 841 return true; 842 843 if (Ty->isPointerType()) 844 return true; 845 846 if (Ty->isReferenceType()) 847 return true; 848 849 if (FreeRegs) 850 NeedsPadding = true; 851 852 return false; 853 } 854 855 return true; 856 } 857 858 ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, 859 unsigned &FreeRegs, 860 bool IsFastCall) const { 861 // FIXME: Set alignment on indirect arguments. 862 if (isAggregateTypeForABI(Ty)) { 863 // Structures with flexible arrays are always indirect. 864 if (const RecordType *RT = Ty->getAs<RecordType>()) { 865 // Structures with either a non-trivial destructor or a non-trivial 866 // copy constructor are always indirect. 867 if (hasNonTrivialDestructorOrCopyConstructor(RT)) 868 return getIndirectResult(Ty, false, FreeRegs); 869 870 if (RT->getDecl()->hasFlexibleArrayMember()) 871 return getIndirectResult(Ty, true, FreeRegs); 872 } 873 874 // Ignore empty structs/unions. 875 if (isEmptyRecord(getContext(), Ty, true)) 876 return ABIArgInfo::getIgnore(); 877 878 llvm::LLVMContext &LLVMContext = getVMContext(); 879 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext); 880 bool NeedsPadding; 881 if (shouldUseInReg(Ty, FreeRegs, IsFastCall, NeedsPadding)) { 882 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32; 883 SmallVector<llvm::Type*, 3> Elements; 884 for (unsigned I = 0; I < SizeInRegs; ++I) 885 Elements.push_back(Int32); 886 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements); 887 return ABIArgInfo::getDirectInReg(Result); 888 } 889 llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : 0; 890 891 // Expand small (<= 128-bit) record types when we know that the stack layout 892 // of those arguments will match the struct. This is important because the 893 // LLVM backend isn't smart enough to remove byval, which inhibits many 894 // optimizations. 895 if (getContext().getTypeSize(Ty) <= 4*32 && 896 canExpandIndirectArgument(Ty, getContext())) 897 return ABIArgInfo::getExpandWithPadding(IsFastCall, PaddingType); 898 899 return getIndirectResult(Ty, true, FreeRegs); 900 } 901 902 if (const VectorType *VT = Ty->getAs<VectorType>()) { 903 // On Darwin, some vectors are passed in memory, we handle this by passing 904 // it as an i8/i16/i32/i64. 905 if (IsDarwinVectorABI) { 906 uint64_t Size = getContext().getTypeSize(Ty); 907 if ((Size == 8 || Size == 16 || Size == 32) || 908 (Size == 64 && VT->getNumElements() == 1)) 909 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 910 Size)); 911 } 912 913 llvm::Type *IRType = CGT.ConvertType(Ty); 914 if (UseX86_MMXType(IRType)) { 915 if (IsMMXDisabled) 916 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 917 64)); 918 ABIArgInfo AAI = ABIArgInfo::getDirect(IRType); 919 AAI.setCoerceToType(llvm::Type::getX86_MMXTy(getVMContext())); 920 return AAI; 921 } 922 923 return ABIArgInfo::getDirect(); 924 } 925 926 927 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 928 Ty = EnumTy->getDecl()->getIntegerType(); 929 930 bool NeedsPadding; 931 bool InReg = shouldUseInReg(Ty, FreeRegs, IsFastCall, NeedsPadding); 932 933 if (Ty->isPromotableIntegerType()) { 934 if (InReg) 935 return ABIArgInfo::getExtendInReg(); 936 return ABIArgInfo::getExtend(); 937 } 938 if (InReg) 939 return ABIArgInfo::getDirectInReg(); 940 return ABIArgInfo::getDirect(); 941 } 942 943 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const { 944 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), 945 FI.getCallingConvention()); 946 947 unsigned CC = FI.getCallingConvention(); 948 bool IsFastCall = CC == llvm::CallingConv::X86_FastCall; 949 unsigned FreeRegs; 950 if (IsFastCall) 951 FreeRegs = 2; 952 else if (FI.getHasRegParm()) 953 FreeRegs = FI.getRegParm(); 954 else 955 FreeRegs = DefaultNumRegisterParameters; 956 957 // If the return value is indirect, then the hidden argument is consuming one 958 // integer register. 959 if (FI.getReturnInfo().isIndirect() && FreeRegs) { 960 --FreeRegs; 961 ABIArgInfo &Old = FI.getReturnInfo(); 962 Old = ABIArgInfo::getIndirectInReg(Old.getIndirectAlign(), 963 Old.getIndirectByVal(), 964 Old.getIndirectRealign()); 965 } 966 967 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 968 it != ie; ++it) 969 it->info = classifyArgumentType(it->type, FreeRegs, IsFastCall); 970 } 971 972 llvm::Value *X86_32ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 973 CodeGenFunction &CGF) const { 974 llvm::Type *BPP = CGF.Int8PtrPtrTy; 975 976 CGBuilderTy &Builder = CGF.Builder; 977 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 978 "ap"); 979 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 980 981 // Compute if the address needs to be aligned 982 unsigned Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity(); 983 Align = getTypeStackAlignInBytes(Ty, Align); 984 Align = std::max(Align, 4U); 985 if (Align > 4) { 986 // addr = (addr + align - 1) & -align; 987 llvm::Value *Offset = 988 llvm::ConstantInt::get(CGF.Int32Ty, Align - 1); 989 Addr = CGF.Builder.CreateGEP(Addr, Offset); 990 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(Addr, 991 CGF.Int32Ty); 992 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -Align); 993 Addr = CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), 994 Addr->getType(), 995 "ap.cur.aligned"); 996 } 997 998 llvm::Type *PTy = 999 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 1000 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 1001 1002 uint64_t Offset = 1003 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, Align); 1004 llvm::Value *NextAddr = 1005 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 1006 "ap.next"); 1007 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 1008 1009 return AddrTyped; 1010 } 1011 1012 void X86_32TargetCodeGenInfo::SetTargetAttributes(const Decl *D, 1013 llvm::GlobalValue *GV, 1014 CodeGen::CodeGenModule &CGM) const { 1015 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) { 1016 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { 1017 // Get the LLVM function. 1018 llvm::Function *Fn = cast<llvm::Function>(GV); 1019 1020 // Now add the 'alignstack' attribute with a value of 16. 1021 llvm::AttrBuilder B; 1022 B.addStackAlignmentAttr(16); 1023 Fn->addAttributes(llvm::AttributeSet::FunctionIndex, 1024 llvm::AttributeSet::get(CGM.getLLVMContext(), 1025 llvm::AttributeSet::FunctionIndex, 1026 B)); 1027 } 1028 } 1029 } 1030 1031 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable( 1032 CodeGen::CodeGenFunction &CGF, 1033 llvm::Value *Address) const { 1034 CodeGen::CGBuilderTy &Builder = CGF.Builder; 1035 1036 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 1037 1038 // 0-7 are the eight integer registers; the order is different 1039 // on Darwin (for EH), but the range is the same. 1040 // 8 is %eip. 1041 AssignToArrayRange(Builder, Address, Four8, 0, 8); 1042 1043 if (CGF.CGM.isTargetDarwin()) { 1044 // 12-16 are st(0..4). Not sure why we stop at 4. 1045 // These have size 16, which is sizeof(long double) on 1046 // platforms with 8-byte alignment for that type. 1047 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16); 1048 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16); 1049 1050 } else { 1051 // 9 is %eflags, which doesn't get a size on Darwin for some 1052 // reason. 1053 Builder.CreateStore(Four8, Builder.CreateConstInBoundsGEP1_32(Address, 9)); 1054 1055 // 11-16 are st(0..5). Not sure why we stop at 5. 1056 // These have size 12, which is sizeof(long double) on 1057 // platforms with 4-byte alignment for that type. 1058 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12); 1059 AssignToArrayRange(Builder, Address, Twelve8, 11, 16); 1060 } 1061 1062 return false; 1063 } 1064 1065 //===----------------------------------------------------------------------===// 1066 // X86-64 ABI Implementation 1067 //===----------------------------------------------------------------------===// 1068 1069 1070 namespace { 1071 /// X86_64ABIInfo - The X86_64 ABI information. 1072 class X86_64ABIInfo : public ABIInfo { 1073 enum Class { 1074 Integer = 0, 1075 SSE, 1076 SSEUp, 1077 X87, 1078 X87Up, 1079 ComplexX87, 1080 NoClass, 1081 Memory 1082 }; 1083 1084 /// merge - Implement the X86_64 ABI merging algorithm. 1085 /// 1086 /// Merge an accumulating classification \arg Accum with a field 1087 /// classification \arg Field. 1088 /// 1089 /// \param Accum - The accumulating classification. This should 1090 /// always be either NoClass or the result of a previous merge 1091 /// call. In addition, this should never be Memory (the caller 1092 /// should just return Memory for the aggregate). 1093 static Class merge(Class Accum, Class Field); 1094 1095 /// postMerge - Implement the X86_64 ABI post merging algorithm. 1096 /// 1097 /// Post merger cleanup, reduces a malformed Hi and Lo pair to 1098 /// final MEMORY or SSE classes when necessary. 1099 /// 1100 /// \param AggregateSize - The size of the current aggregate in 1101 /// the classification process. 1102 /// 1103 /// \param Lo - The classification for the parts of the type 1104 /// residing in the low word of the containing object. 1105 /// 1106 /// \param Hi - The classification for the parts of the type 1107 /// residing in the higher words of the containing object. 1108 /// 1109 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const; 1110 1111 /// classify - Determine the x86_64 register classes in which the 1112 /// given type T should be passed. 1113 /// 1114 /// \param Lo - The classification for the parts of the type 1115 /// residing in the low word of the containing object. 1116 /// 1117 /// \param Hi - The classification for the parts of the type 1118 /// residing in the high word of the containing object. 1119 /// 1120 /// \param OffsetBase - The bit offset of this type in the 1121 /// containing object. Some parameters are classified different 1122 /// depending on whether they straddle an eightbyte boundary. 1123 /// 1124 /// If a word is unused its result will be NoClass; if a type should 1125 /// be passed in Memory then at least the classification of \arg Lo 1126 /// will be Memory. 1127 /// 1128 /// The \arg Lo class will be NoClass iff the argument is ignored. 1129 /// 1130 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will 1131 /// also be ComplexX87. 1132 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi) const; 1133 1134 llvm::Type *GetByteVectorType(QualType Ty) const; 1135 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType, 1136 unsigned IROffset, QualType SourceTy, 1137 unsigned SourceOffset) const; 1138 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType, 1139 unsigned IROffset, QualType SourceTy, 1140 unsigned SourceOffset) const; 1141 1142 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 1143 /// such that the argument will be returned in memory. 1144 ABIArgInfo getIndirectReturnResult(QualType Ty) const; 1145 1146 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 1147 /// such that the argument will be passed in memory. 1148 /// 1149 /// \param freeIntRegs - The number of free integer registers remaining 1150 /// available. 1151 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const; 1152 1153 ABIArgInfo classifyReturnType(QualType RetTy) const; 1154 1155 ABIArgInfo classifyArgumentType(QualType Ty, 1156 unsigned freeIntRegs, 1157 unsigned &neededInt, 1158 unsigned &neededSSE) const; 1159 1160 bool IsIllegalVectorType(QualType Ty) const; 1161 1162 /// The 0.98 ABI revision clarified a lot of ambiguities, 1163 /// unfortunately in ways that were not always consistent with 1164 /// certain previous compilers. In particular, platforms which 1165 /// required strict binary compatibility with older versions of GCC 1166 /// may need to exempt themselves. 1167 bool honorsRevision0_98() const { 1168 return !getContext().getTargetInfo().getTriple().isOSDarwin(); 1169 } 1170 1171 bool HasAVX; 1172 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on 1173 // 64-bit hardware. 1174 bool Has64BitPointers; 1175 1176 public: 1177 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, bool hasavx) : 1178 ABIInfo(CGT), HasAVX(hasavx), 1179 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) { 1180 } 1181 1182 bool isPassedUsingAVXType(QualType type) const { 1183 unsigned neededInt, neededSSE; 1184 // The freeIntRegs argument doesn't matter here. 1185 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE); 1186 if (info.isDirect()) { 1187 llvm::Type *ty = info.getCoerceToType(); 1188 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty)) 1189 return (vectorTy->getBitWidth() > 128); 1190 } 1191 return false; 1192 } 1193 1194 virtual void computeInfo(CGFunctionInfo &FI) const; 1195 1196 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 1197 CodeGenFunction &CGF) const; 1198 }; 1199 1200 /// WinX86_64ABIInfo - The Windows X86_64 ABI information. 1201 class WinX86_64ABIInfo : public ABIInfo { 1202 1203 ABIArgInfo classify(QualType Ty) const; 1204 1205 public: 1206 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 1207 1208 virtual void computeInfo(CGFunctionInfo &FI) const; 1209 1210 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 1211 CodeGenFunction &CGF) const; 1212 }; 1213 1214 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo { 1215 public: 1216 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 1217 : TargetCodeGenInfo(new X86_64ABIInfo(CGT, HasAVX)) {} 1218 1219 const X86_64ABIInfo &getABIInfo() const { 1220 return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo()); 1221 } 1222 1223 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 1224 return 7; 1225 } 1226 1227 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 1228 llvm::Value *Address) const { 1229 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 1230 1231 // 0-15 are the 16 integer registers. 1232 // 16 is %rip. 1233 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); 1234 return false; 1235 } 1236 1237 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 1238 StringRef Constraint, 1239 llvm::Type* Ty) const { 1240 return X86AdjustInlineAsmType(CGF, Constraint, Ty); 1241 } 1242 1243 bool isNoProtoCallVariadic(const CallArgList &args, 1244 const FunctionNoProtoType *fnType) const { 1245 // The default CC on x86-64 sets %al to the number of SSA 1246 // registers used, and GCC sets this when calling an unprototyped 1247 // function, so we override the default behavior. However, don't do 1248 // that when AVX types are involved: the ABI explicitly states it is 1249 // undefined, and it doesn't work in practice because of how the ABI 1250 // defines varargs anyway. 1251 if (fnType->getCallConv() == CC_Default || fnType->getCallConv() == CC_C) { 1252 bool HasAVXType = false; 1253 for (CallArgList::const_iterator 1254 it = args.begin(), ie = args.end(); it != ie; ++it) { 1255 if (getABIInfo().isPassedUsingAVXType(it->Ty)) { 1256 HasAVXType = true; 1257 break; 1258 } 1259 } 1260 1261 if (!HasAVXType) 1262 return true; 1263 } 1264 1265 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType); 1266 } 1267 1268 }; 1269 1270 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo { 1271 public: 1272 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 1273 : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {} 1274 1275 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 1276 return 7; 1277 } 1278 1279 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 1280 llvm::Value *Address) const { 1281 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 1282 1283 // 0-15 are the 16 integer registers. 1284 // 16 is %rip. 1285 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); 1286 return false; 1287 } 1288 }; 1289 1290 } 1291 1292 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, 1293 Class &Hi) const { 1294 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done: 1295 // 1296 // (a) If one of the classes is Memory, the whole argument is passed in 1297 // memory. 1298 // 1299 // (b) If X87UP is not preceded by X87, the whole argument is passed in 1300 // memory. 1301 // 1302 // (c) If the size of the aggregate exceeds two eightbytes and the first 1303 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole 1304 // argument is passed in memory. NOTE: This is necessary to keep the 1305 // ABI working for processors that don't support the __m256 type. 1306 // 1307 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE. 1308 // 1309 // Some of these are enforced by the merging logic. Others can arise 1310 // only with unions; for example: 1311 // union { _Complex double; unsigned; } 1312 // 1313 // Note that clauses (b) and (c) were added in 0.98. 1314 // 1315 if (Hi == Memory) 1316 Lo = Memory; 1317 if (Hi == X87Up && Lo != X87 && honorsRevision0_98()) 1318 Lo = Memory; 1319 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp)) 1320 Lo = Memory; 1321 if (Hi == SSEUp && Lo != SSE) 1322 Hi = SSE; 1323 } 1324 1325 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) { 1326 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is 1327 // classified recursively so that always two fields are 1328 // considered. The resulting class is calculated according to 1329 // the classes of the fields in the eightbyte: 1330 // 1331 // (a) If both classes are equal, this is the resulting class. 1332 // 1333 // (b) If one of the classes is NO_CLASS, the resulting class is 1334 // the other class. 1335 // 1336 // (c) If one of the classes is MEMORY, the result is the MEMORY 1337 // class. 1338 // 1339 // (d) If one of the classes is INTEGER, the result is the 1340 // INTEGER. 1341 // 1342 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class, 1343 // MEMORY is used as class. 1344 // 1345 // (f) Otherwise class SSE is used. 1346 1347 // Accum should never be memory (we should have returned) or 1348 // ComplexX87 (because this cannot be passed in a structure). 1349 assert((Accum != Memory && Accum != ComplexX87) && 1350 "Invalid accumulated classification during merge."); 1351 if (Accum == Field || Field == NoClass) 1352 return Accum; 1353 if (Field == Memory) 1354 return Memory; 1355 if (Accum == NoClass) 1356 return Field; 1357 if (Accum == Integer || Field == Integer) 1358 return Integer; 1359 if (Field == X87 || Field == X87Up || Field == ComplexX87 || 1360 Accum == X87 || Accum == X87Up) 1361 return Memory; 1362 return SSE; 1363 } 1364 1365 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase, 1366 Class &Lo, Class &Hi) const { 1367 // FIXME: This code can be simplified by introducing a simple value class for 1368 // Class pairs with appropriate constructor methods for the various 1369 // situations. 1370 1371 // FIXME: Some of the split computations are wrong; unaligned vectors 1372 // shouldn't be passed in registers for example, so there is no chance they 1373 // can straddle an eightbyte. Verify & simplify. 1374 1375 Lo = Hi = NoClass; 1376 1377 Class &Current = OffsetBase < 64 ? Lo : Hi; 1378 Current = Memory; 1379 1380 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 1381 BuiltinType::Kind k = BT->getKind(); 1382 1383 if (k == BuiltinType::Void) { 1384 Current = NoClass; 1385 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) { 1386 Lo = Integer; 1387 Hi = Integer; 1388 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) { 1389 Current = Integer; 1390 } else if ((k == BuiltinType::Float || k == BuiltinType::Double) || 1391 (k == BuiltinType::LongDouble && 1392 getContext().getTargetInfo().getTriple().getOS() == 1393 llvm::Triple::NaCl)) { 1394 Current = SSE; 1395 } else if (k == BuiltinType::LongDouble) { 1396 Lo = X87; 1397 Hi = X87Up; 1398 } 1399 // FIXME: _Decimal32 and _Decimal64 are SSE. 1400 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp). 1401 return; 1402 } 1403 1404 if (const EnumType *ET = Ty->getAs<EnumType>()) { 1405 // Classify the underlying integer type. 1406 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi); 1407 return; 1408 } 1409 1410 if (Ty->hasPointerRepresentation()) { 1411 Current = Integer; 1412 return; 1413 } 1414 1415 if (Ty->isMemberPointerType()) { 1416 if (Ty->isMemberFunctionPointerType() && Has64BitPointers) 1417 Lo = Hi = Integer; 1418 else 1419 Current = Integer; 1420 return; 1421 } 1422 1423 if (const VectorType *VT = Ty->getAs<VectorType>()) { 1424 uint64_t Size = getContext().getTypeSize(VT); 1425 if (Size == 32) { 1426 // gcc passes all <4 x char>, <2 x short>, <1 x int>, <1 x 1427 // float> as integer. 1428 Current = Integer; 1429 1430 // If this type crosses an eightbyte boundary, it should be 1431 // split. 1432 uint64_t EB_Real = (OffsetBase) / 64; 1433 uint64_t EB_Imag = (OffsetBase + Size - 1) / 64; 1434 if (EB_Real != EB_Imag) 1435 Hi = Lo; 1436 } else if (Size == 64) { 1437 // gcc passes <1 x double> in memory. :( 1438 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) 1439 return; 1440 1441 // gcc passes <1 x long long> as INTEGER. 1442 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::LongLong) || 1443 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULongLong) || 1444 VT->getElementType()->isSpecificBuiltinType(BuiltinType::Long) || 1445 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULong)) 1446 Current = Integer; 1447 else 1448 Current = SSE; 1449 1450 // If this type crosses an eightbyte boundary, it should be 1451 // split. 1452 if (OffsetBase && OffsetBase != 64) 1453 Hi = Lo; 1454 } else if (Size == 128 || (HasAVX && Size == 256)) { 1455 // Arguments of 256-bits are split into four eightbyte chunks. The 1456 // least significant one belongs to class SSE and all the others to class 1457 // SSEUP. The original Lo and Hi design considers that types can't be 1458 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense. 1459 // This design isn't correct for 256-bits, but since there're no cases 1460 // where the upper parts would need to be inspected, avoid adding 1461 // complexity and just consider Hi to match the 64-256 part. 1462 Lo = SSE; 1463 Hi = SSEUp; 1464 } 1465 return; 1466 } 1467 1468 if (const ComplexType *CT = Ty->getAs<ComplexType>()) { 1469 QualType ET = getContext().getCanonicalType(CT->getElementType()); 1470 1471 uint64_t Size = getContext().getTypeSize(Ty); 1472 if (ET->isIntegralOrEnumerationType()) { 1473 if (Size <= 64) 1474 Current = Integer; 1475 else if (Size <= 128) 1476 Lo = Hi = Integer; 1477 } else if (ET == getContext().FloatTy) 1478 Current = SSE; 1479 else if (ET == getContext().DoubleTy || 1480 (ET == getContext().LongDoubleTy && 1481 getContext().getTargetInfo().getTriple().getOS() == 1482 llvm::Triple::NaCl)) 1483 Lo = Hi = SSE; 1484 else if (ET == getContext().LongDoubleTy) 1485 Current = ComplexX87; 1486 1487 // If this complex type crosses an eightbyte boundary then it 1488 // should be split. 1489 uint64_t EB_Real = (OffsetBase) / 64; 1490 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64; 1491 if (Hi == NoClass && EB_Real != EB_Imag) 1492 Hi = Lo; 1493 1494 return; 1495 } 1496 1497 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) { 1498 // Arrays are treated like structures. 1499 1500 uint64_t Size = getContext().getTypeSize(Ty); 1501 1502 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger 1503 // than four eightbytes, ..., it has class MEMORY. 1504 if (Size > 256) 1505 return; 1506 1507 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned 1508 // fields, it has class MEMORY. 1509 // 1510 // Only need to check alignment of array base. 1511 if (OffsetBase % getContext().getTypeAlign(AT->getElementType())) 1512 return; 1513 1514 // Otherwise implement simplified merge. We could be smarter about 1515 // this, but it isn't worth it and would be harder to verify. 1516 Current = NoClass; 1517 uint64_t EltSize = getContext().getTypeSize(AT->getElementType()); 1518 uint64_t ArraySize = AT->getSize().getZExtValue(); 1519 1520 // The only case a 256-bit wide vector could be used is when the array 1521 // contains a single 256-bit element. Since Lo and Hi logic isn't extended 1522 // to work for sizes wider than 128, early check and fallback to memory. 1523 if (Size > 128 && EltSize != 256) 1524 return; 1525 1526 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) { 1527 Class FieldLo, FieldHi; 1528 classify(AT->getElementType(), Offset, FieldLo, FieldHi); 1529 Lo = merge(Lo, FieldLo); 1530 Hi = merge(Hi, FieldHi); 1531 if (Lo == Memory || Hi == Memory) 1532 break; 1533 } 1534 1535 postMerge(Size, Lo, Hi); 1536 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification."); 1537 return; 1538 } 1539 1540 if (const RecordType *RT = Ty->getAs<RecordType>()) { 1541 uint64_t Size = getContext().getTypeSize(Ty); 1542 1543 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger 1544 // than four eightbytes, ..., it has class MEMORY. 1545 if (Size > 256) 1546 return; 1547 1548 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial 1549 // copy constructor or a non-trivial destructor, it is passed by invisible 1550 // reference. 1551 if (hasNonTrivialDestructorOrCopyConstructor(RT)) 1552 return; 1553 1554 const RecordDecl *RD = RT->getDecl(); 1555 1556 // Assume variable sized types are passed in memory. 1557 if (RD->hasFlexibleArrayMember()) 1558 return; 1559 1560 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 1561 1562 // Reset Lo class, this will be recomputed. 1563 Current = NoClass; 1564 1565 // If this is a C++ record, classify the bases first. 1566 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 1567 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 1568 e = CXXRD->bases_end(); i != e; ++i) { 1569 assert(!i->isVirtual() && !i->getType()->isDependentType() && 1570 "Unexpected base class!"); 1571 const CXXRecordDecl *Base = 1572 cast<CXXRecordDecl>(i->getType()->getAs<RecordType>()->getDecl()); 1573 1574 // Classify this field. 1575 // 1576 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a 1577 // single eightbyte, each is classified separately. Each eightbyte gets 1578 // initialized to class NO_CLASS. 1579 Class FieldLo, FieldHi; 1580 uint64_t Offset = 1581 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base)); 1582 classify(i->getType(), Offset, FieldLo, FieldHi); 1583 Lo = merge(Lo, FieldLo); 1584 Hi = merge(Hi, FieldHi); 1585 if (Lo == Memory || Hi == Memory) 1586 break; 1587 } 1588 } 1589 1590 // Classify the fields one at a time, merging the results. 1591 unsigned idx = 0; 1592 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 1593 i != e; ++i, ++idx) { 1594 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx); 1595 bool BitField = i->isBitField(); 1596 1597 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than 1598 // four eightbytes, or it contains unaligned fields, it has class MEMORY. 1599 // 1600 // The only case a 256-bit wide vector could be used is when the struct 1601 // contains a single 256-bit element. Since Lo and Hi logic isn't extended 1602 // to work for sizes wider than 128, early check and fallback to memory. 1603 // 1604 if (Size > 128 && getContext().getTypeSize(i->getType()) != 256) { 1605 Lo = Memory; 1606 return; 1607 } 1608 // Note, skip this test for bit-fields, see below. 1609 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) { 1610 Lo = Memory; 1611 return; 1612 } 1613 1614 // Classify this field. 1615 // 1616 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate 1617 // exceeds a single eightbyte, each is classified 1618 // separately. Each eightbyte gets initialized to class 1619 // NO_CLASS. 1620 Class FieldLo, FieldHi; 1621 1622 // Bit-fields require special handling, they do not force the 1623 // structure to be passed in memory even if unaligned, and 1624 // therefore they can straddle an eightbyte. 1625 if (BitField) { 1626 // Ignore padding bit-fields. 1627 if (i->isUnnamedBitfield()) 1628 continue; 1629 1630 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx); 1631 uint64_t Size = i->getBitWidthValue(getContext()); 1632 1633 uint64_t EB_Lo = Offset / 64; 1634 uint64_t EB_Hi = (Offset + Size - 1) / 64; 1635 FieldLo = FieldHi = NoClass; 1636 if (EB_Lo) { 1637 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes."); 1638 FieldLo = NoClass; 1639 FieldHi = Integer; 1640 } else { 1641 FieldLo = Integer; 1642 FieldHi = EB_Hi ? Integer : NoClass; 1643 } 1644 } else 1645 classify(i->getType(), Offset, FieldLo, FieldHi); 1646 Lo = merge(Lo, FieldLo); 1647 Hi = merge(Hi, FieldHi); 1648 if (Lo == Memory || Hi == Memory) 1649 break; 1650 } 1651 1652 postMerge(Size, Lo, Hi); 1653 } 1654 } 1655 1656 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const { 1657 // If this is a scalar LLVM value then assume LLVM will pass it in the right 1658 // place naturally. 1659 if (!isAggregateTypeForABI(Ty)) { 1660 // Treat an enum type as its underlying type. 1661 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 1662 Ty = EnumTy->getDecl()->getIntegerType(); 1663 1664 return (Ty->isPromotableIntegerType() ? 1665 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 1666 } 1667 1668 return ABIArgInfo::getIndirect(0); 1669 } 1670 1671 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const { 1672 if (const VectorType *VecTy = Ty->getAs<VectorType>()) { 1673 uint64_t Size = getContext().getTypeSize(VecTy); 1674 unsigned LargestVector = HasAVX ? 256 : 128; 1675 if (Size <= 64 || Size > LargestVector) 1676 return true; 1677 } 1678 1679 return false; 1680 } 1681 1682 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty, 1683 unsigned freeIntRegs) const { 1684 // If this is a scalar LLVM value then assume LLVM will pass it in the right 1685 // place naturally. 1686 // 1687 // This assumption is optimistic, as there could be free registers available 1688 // when we need to pass this argument in memory, and LLVM could try to pass 1689 // the argument in the free register. This does not seem to happen currently, 1690 // but this code would be much safer if we could mark the argument with 1691 // 'onstack'. See PR12193. 1692 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) { 1693 // Treat an enum type as its underlying type. 1694 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 1695 Ty = EnumTy->getDecl()->getIntegerType(); 1696 1697 return (Ty->isPromotableIntegerType() ? 1698 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 1699 } 1700 1701 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 1702 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 1703 1704 // Compute the byval alignment. We specify the alignment of the byval in all 1705 // cases so that the mid-level optimizer knows the alignment of the byval. 1706 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U); 1707 1708 // Attempt to avoid passing indirect results using byval when possible. This 1709 // is important for good codegen. 1710 // 1711 // We do this by coercing the value into a scalar type which the backend can 1712 // handle naturally (i.e., without using byval). 1713 // 1714 // For simplicity, we currently only do this when we have exhausted all of the 1715 // free integer registers. Doing this when there are free integer registers 1716 // would require more care, as we would have to ensure that the coerced value 1717 // did not claim the unused register. That would require either reording the 1718 // arguments to the function (so that any subsequent inreg values came first), 1719 // or only doing this optimization when there were no following arguments that 1720 // might be inreg. 1721 // 1722 // We currently expect it to be rare (particularly in well written code) for 1723 // arguments to be passed on the stack when there are still free integer 1724 // registers available (this would typically imply large structs being passed 1725 // by value), so this seems like a fair tradeoff for now. 1726 // 1727 // We can revisit this if the backend grows support for 'onstack' parameter 1728 // attributes. See PR12193. 1729 if (freeIntRegs == 0) { 1730 uint64_t Size = getContext().getTypeSize(Ty); 1731 1732 // If this type fits in an eightbyte, coerce it into the matching integral 1733 // type, which will end up on the stack (with alignment 8). 1734 if (Align == 8 && Size <= 64) 1735 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 1736 Size)); 1737 } 1738 1739 return ABIArgInfo::getIndirect(Align); 1740 } 1741 1742 /// GetByteVectorType - The ABI specifies that a value should be passed in an 1743 /// full vector XMM/YMM register. Pick an LLVM IR type that will be passed as a 1744 /// vector register. 1745 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const { 1746 llvm::Type *IRType = CGT.ConvertType(Ty); 1747 1748 // Wrapper structs that just contain vectors are passed just like vectors, 1749 // strip them off if present. 1750 llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType); 1751 while (STy && STy->getNumElements() == 1) { 1752 IRType = STy->getElementType(0); 1753 STy = dyn_cast<llvm::StructType>(IRType); 1754 } 1755 1756 // If the preferred type is a 16-byte vector, prefer to pass it. 1757 if (llvm::VectorType *VT = dyn_cast<llvm::VectorType>(IRType)){ 1758 llvm::Type *EltTy = VT->getElementType(); 1759 unsigned BitWidth = VT->getBitWidth(); 1760 if ((BitWidth >= 128 && BitWidth <= 256) && 1761 (EltTy->isFloatTy() || EltTy->isDoubleTy() || 1762 EltTy->isIntegerTy(8) || EltTy->isIntegerTy(16) || 1763 EltTy->isIntegerTy(32) || EltTy->isIntegerTy(64) || 1764 EltTy->isIntegerTy(128))) 1765 return VT; 1766 } 1767 1768 return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()), 2); 1769 } 1770 1771 /// BitsContainNoUserData - Return true if the specified [start,end) bit range 1772 /// is known to either be off the end of the specified type or being in 1773 /// alignment padding. The user type specified is known to be at most 128 bits 1774 /// in size, and have passed through X86_64ABIInfo::classify with a successful 1775 /// classification that put one of the two halves in the INTEGER class. 1776 /// 1777 /// It is conservatively correct to return false. 1778 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit, 1779 unsigned EndBit, ASTContext &Context) { 1780 // If the bytes being queried are off the end of the type, there is no user 1781 // data hiding here. This handles analysis of builtins, vectors and other 1782 // types that don't contain interesting padding. 1783 unsigned TySize = (unsigned)Context.getTypeSize(Ty); 1784 if (TySize <= StartBit) 1785 return true; 1786 1787 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) { 1788 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType()); 1789 unsigned NumElts = (unsigned)AT->getSize().getZExtValue(); 1790 1791 // Check each element to see if the element overlaps with the queried range. 1792 for (unsigned i = 0; i != NumElts; ++i) { 1793 // If the element is after the span we care about, then we're done.. 1794 unsigned EltOffset = i*EltSize; 1795 if (EltOffset >= EndBit) break; 1796 1797 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0; 1798 if (!BitsContainNoUserData(AT->getElementType(), EltStart, 1799 EndBit-EltOffset, Context)) 1800 return false; 1801 } 1802 // If it overlaps no elements, then it is safe to process as padding. 1803 return true; 1804 } 1805 1806 if (const RecordType *RT = Ty->getAs<RecordType>()) { 1807 const RecordDecl *RD = RT->getDecl(); 1808 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD); 1809 1810 // If this is a C++ record, check the bases first. 1811 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 1812 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 1813 e = CXXRD->bases_end(); i != e; ++i) { 1814 assert(!i->isVirtual() && !i->getType()->isDependentType() && 1815 "Unexpected base class!"); 1816 const CXXRecordDecl *Base = 1817 cast<CXXRecordDecl>(i->getType()->getAs<RecordType>()->getDecl()); 1818 1819 // If the base is after the span we care about, ignore it. 1820 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base)); 1821 if (BaseOffset >= EndBit) continue; 1822 1823 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0; 1824 if (!BitsContainNoUserData(i->getType(), BaseStart, 1825 EndBit-BaseOffset, Context)) 1826 return false; 1827 } 1828 } 1829 1830 // Verify that no field has data that overlaps the region of interest. Yes 1831 // this could be sped up a lot by being smarter about queried fields, 1832 // however we're only looking at structs up to 16 bytes, so we don't care 1833 // much. 1834 unsigned idx = 0; 1835 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 1836 i != e; ++i, ++idx) { 1837 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx); 1838 1839 // If we found a field after the region we care about, then we're done. 1840 if (FieldOffset >= EndBit) break; 1841 1842 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0; 1843 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset, 1844 Context)) 1845 return false; 1846 } 1847 1848 // If nothing in this record overlapped the area of interest, then we're 1849 // clean. 1850 return true; 1851 } 1852 1853 return false; 1854 } 1855 1856 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a 1857 /// float member at the specified offset. For example, {int,{float}} has a 1858 /// float at offset 4. It is conservatively correct for this routine to return 1859 /// false. 1860 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset, 1861 const llvm::DataLayout &TD) { 1862 // Base case if we find a float. 1863 if (IROffset == 0 && IRType->isFloatTy()) 1864 return true; 1865 1866 // If this is a struct, recurse into the field at the specified offset. 1867 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) { 1868 const llvm::StructLayout *SL = TD.getStructLayout(STy); 1869 unsigned Elt = SL->getElementContainingOffset(IROffset); 1870 IROffset -= SL->getElementOffset(Elt); 1871 return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD); 1872 } 1873 1874 // If this is an array, recurse into the field at the specified offset. 1875 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) { 1876 llvm::Type *EltTy = ATy->getElementType(); 1877 unsigned EltSize = TD.getTypeAllocSize(EltTy); 1878 IROffset -= IROffset/EltSize*EltSize; 1879 return ContainsFloatAtOffset(EltTy, IROffset, TD); 1880 } 1881 1882 return false; 1883 } 1884 1885 1886 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the 1887 /// low 8 bytes of an XMM register, corresponding to the SSE class. 1888 llvm::Type *X86_64ABIInfo:: 1889 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset, 1890 QualType SourceTy, unsigned SourceOffset) const { 1891 // The only three choices we have are either double, <2 x float>, or float. We 1892 // pass as float if the last 4 bytes is just padding. This happens for 1893 // structs that contain 3 floats. 1894 if (BitsContainNoUserData(SourceTy, SourceOffset*8+32, 1895 SourceOffset*8+64, getContext())) 1896 return llvm::Type::getFloatTy(getVMContext()); 1897 1898 // We want to pass as <2 x float> if the LLVM IR type contains a float at 1899 // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the 1900 // case. 1901 if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) && 1902 ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout())) 1903 return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2); 1904 1905 return llvm::Type::getDoubleTy(getVMContext()); 1906 } 1907 1908 1909 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in 1910 /// an 8-byte GPR. This means that we either have a scalar or we are talking 1911 /// about the high or low part of an up-to-16-byte struct. This routine picks 1912 /// the best LLVM IR type to represent this, which may be i64 or may be anything 1913 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*, 1914 /// etc). 1915 /// 1916 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for 1917 /// the source type. IROffset is an offset in bytes into the LLVM IR type that 1918 /// the 8-byte value references. PrefType may be null. 1919 /// 1920 /// SourceTy is the source level type for the entire argument. SourceOffset is 1921 /// an offset into this that we're processing (which is always either 0 or 8). 1922 /// 1923 llvm::Type *X86_64ABIInfo:: 1924 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset, 1925 QualType SourceTy, unsigned SourceOffset) const { 1926 // If we're dealing with an un-offset LLVM IR type, then it means that we're 1927 // returning an 8-byte unit starting with it. See if we can safely use it. 1928 if (IROffset == 0) { 1929 // Pointers and int64's always fill the 8-byte unit. 1930 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) || 1931 IRType->isIntegerTy(64)) 1932 return IRType; 1933 1934 // If we have a 1/2/4-byte integer, we can use it only if the rest of the 1935 // goodness in the source type is just tail padding. This is allowed to 1936 // kick in for struct {double,int} on the int, but not on 1937 // struct{double,int,int} because we wouldn't return the second int. We 1938 // have to do this analysis on the source type because we can't depend on 1939 // unions being lowered a specific way etc. 1940 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) || 1941 IRType->isIntegerTy(32) || 1942 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) { 1943 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 : 1944 cast<llvm::IntegerType>(IRType)->getBitWidth(); 1945 1946 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth, 1947 SourceOffset*8+64, getContext())) 1948 return IRType; 1949 } 1950 } 1951 1952 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) { 1953 // If this is a struct, recurse into the field at the specified offset. 1954 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy); 1955 if (IROffset < SL->getSizeInBytes()) { 1956 unsigned FieldIdx = SL->getElementContainingOffset(IROffset); 1957 IROffset -= SL->getElementOffset(FieldIdx); 1958 1959 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset, 1960 SourceTy, SourceOffset); 1961 } 1962 } 1963 1964 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) { 1965 llvm::Type *EltTy = ATy->getElementType(); 1966 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy); 1967 unsigned EltOffset = IROffset/EltSize*EltSize; 1968 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy, 1969 SourceOffset); 1970 } 1971 1972 // Okay, we don't have any better idea of what to pass, so we pass this in an 1973 // integer register that isn't too big to fit the rest of the struct. 1974 unsigned TySizeInBytes = 1975 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity(); 1976 1977 assert(TySizeInBytes != SourceOffset && "Empty field?"); 1978 1979 // It is always safe to classify this as an integer type up to i64 that 1980 // isn't larger than the structure. 1981 return llvm::IntegerType::get(getVMContext(), 1982 std::min(TySizeInBytes-SourceOffset, 8U)*8); 1983 } 1984 1985 1986 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally 1987 /// be used as elements of a two register pair to pass or return, return a 1988 /// first class aggregate to represent them. For example, if the low part of 1989 /// a by-value argument should be passed as i32* and the high part as float, 1990 /// return {i32*, float}. 1991 static llvm::Type * 1992 GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi, 1993 const llvm::DataLayout &TD) { 1994 // In order to correctly satisfy the ABI, we need to the high part to start 1995 // at offset 8. If the high and low parts we inferred are both 4-byte types 1996 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have 1997 // the second element at offset 8. Check for this: 1998 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo); 1999 unsigned HiAlign = TD.getABITypeAlignment(Hi); 2000 unsigned HiStart = llvm::DataLayout::RoundUpAlignment(LoSize, HiAlign); 2001 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!"); 2002 2003 // To handle this, we have to increase the size of the low part so that the 2004 // second element will start at an 8 byte offset. We can't increase the size 2005 // of the second element because it might make us access off the end of the 2006 // struct. 2007 if (HiStart != 8) { 2008 // There are only two sorts of types the ABI generation code can produce for 2009 // the low part of a pair that aren't 8 bytes in size: float or i8/i16/i32. 2010 // Promote these to a larger type. 2011 if (Lo->isFloatTy()) 2012 Lo = llvm::Type::getDoubleTy(Lo->getContext()); 2013 else { 2014 assert(Lo->isIntegerTy() && "Invalid/unknown lo type"); 2015 Lo = llvm::Type::getInt64Ty(Lo->getContext()); 2016 } 2017 } 2018 2019 llvm::StructType *Result = llvm::StructType::get(Lo, Hi, NULL); 2020 2021 2022 // Verify that the second element is at an 8-byte offset. 2023 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 && 2024 "Invalid x86-64 argument pair!"); 2025 return Result; 2026 } 2027 2028 ABIArgInfo X86_64ABIInfo:: 2029 classifyReturnType(QualType RetTy) const { 2030 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the 2031 // classification algorithm. 2032 X86_64ABIInfo::Class Lo, Hi; 2033 classify(RetTy, 0, Lo, Hi); 2034 2035 // Check some invariants. 2036 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification."); 2037 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification."); 2038 2039 llvm::Type *ResType = 0; 2040 switch (Lo) { 2041 case NoClass: 2042 if (Hi == NoClass) 2043 return ABIArgInfo::getIgnore(); 2044 // If the low part is just padding, it takes no register, leave ResType 2045 // null. 2046 assert((Hi == SSE || Hi == Integer || Hi == X87Up) && 2047 "Unknown missing lo part"); 2048 break; 2049 2050 case SSEUp: 2051 case X87Up: 2052 llvm_unreachable("Invalid classification for lo word."); 2053 2054 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via 2055 // hidden argument. 2056 case Memory: 2057 return getIndirectReturnResult(RetTy); 2058 2059 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next 2060 // available register of the sequence %rax, %rdx is used. 2061 case Integer: 2062 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0); 2063 2064 // If we have a sign or zero extended integer, make sure to return Extend 2065 // so that the parameter gets the right LLVM IR attributes. 2066 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) { 2067 // Treat an enum type as its underlying type. 2068 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 2069 RetTy = EnumTy->getDecl()->getIntegerType(); 2070 2071 if (RetTy->isIntegralOrEnumerationType() && 2072 RetTy->isPromotableIntegerType()) 2073 return ABIArgInfo::getExtend(); 2074 } 2075 break; 2076 2077 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next 2078 // available SSE register of the sequence %xmm0, %xmm1 is used. 2079 case SSE: 2080 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0); 2081 break; 2082 2083 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is 2084 // returned on the X87 stack in %st0 as 80-bit x87 number. 2085 case X87: 2086 ResType = llvm::Type::getX86_FP80Ty(getVMContext()); 2087 break; 2088 2089 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real 2090 // part of the value is returned in %st0 and the imaginary part in 2091 // %st1. 2092 case ComplexX87: 2093 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification."); 2094 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()), 2095 llvm::Type::getX86_FP80Ty(getVMContext()), 2096 NULL); 2097 break; 2098 } 2099 2100 llvm::Type *HighPart = 0; 2101 switch (Hi) { 2102 // Memory was handled previously and X87 should 2103 // never occur as a hi class. 2104 case Memory: 2105 case X87: 2106 llvm_unreachable("Invalid classification for hi word."); 2107 2108 case ComplexX87: // Previously handled. 2109 case NoClass: 2110 break; 2111 2112 case Integer: 2113 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2114 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2115 return ABIArgInfo::getDirect(HighPart, 8); 2116 break; 2117 case SSE: 2118 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2119 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2120 return ABIArgInfo::getDirect(HighPart, 8); 2121 break; 2122 2123 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte 2124 // is passed in the next available eightbyte chunk if the last used 2125 // vector register. 2126 // 2127 // SSEUP should always be preceded by SSE, just widen. 2128 case SSEUp: 2129 assert(Lo == SSE && "Unexpected SSEUp classification."); 2130 ResType = GetByteVectorType(RetTy); 2131 break; 2132 2133 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is 2134 // returned together with the previous X87 value in %st0. 2135 case X87Up: 2136 // If X87Up is preceded by X87, we don't need to do 2137 // anything. However, in some cases with unions it may not be 2138 // preceded by X87. In such situations we follow gcc and pass the 2139 // extra bits in an SSE reg. 2140 if (Lo != X87) { 2141 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2142 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2143 return ABIArgInfo::getDirect(HighPart, 8); 2144 } 2145 break; 2146 } 2147 2148 // If a high part was specified, merge it together with the low part. It is 2149 // known to pass in the high eightbyte of the result. We do this by forming a 2150 // first class struct aggregate with the high and low part: {low, high} 2151 if (HighPart) 2152 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout()); 2153 2154 return ABIArgInfo::getDirect(ResType); 2155 } 2156 2157 ABIArgInfo X86_64ABIInfo::classifyArgumentType( 2158 QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE) 2159 const 2160 { 2161 X86_64ABIInfo::Class Lo, Hi; 2162 classify(Ty, 0, Lo, Hi); 2163 2164 // Check some invariants. 2165 // FIXME: Enforce these by construction. 2166 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification."); 2167 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification."); 2168 2169 neededInt = 0; 2170 neededSSE = 0; 2171 llvm::Type *ResType = 0; 2172 switch (Lo) { 2173 case NoClass: 2174 if (Hi == NoClass) 2175 return ABIArgInfo::getIgnore(); 2176 // If the low part is just padding, it takes no register, leave ResType 2177 // null. 2178 assert((Hi == SSE || Hi == Integer || Hi == X87Up) && 2179 "Unknown missing lo part"); 2180 break; 2181 2182 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument 2183 // on the stack. 2184 case Memory: 2185 2186 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or 2187 // COMPLEX_X87, it is passed in memory. 2188 case X87: 2189 case ComplexX87: 2190 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 2191 ++neededInt; 2192 return getIndirectResult(Ty, freeIntRegs); 2193 2194 case SSEUp: 2195 case X87Up: 2196 llvm_unreachable("Invalid classification for lo word."); 2197 2198 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next 2199 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8 2200 // and %r9 is used. 2201 case Integer: 2202 ++neededInt; 2203 2204 // Pick an 8-byte type based on the preferred type. 2205 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0); 2206 2207 // If we have a sign or zero extended integer, make sure to return Extend 2208 // so that the parameter gets the right LLVM IR attributes. 2209 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) { 2210 // Treat an enum type as its underlying type. 2211 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2212 Ty = EnumTy->getDecl()->getIntegerType(); 2213 2214 if (Ty->isIntegralOrEnumerationType() && 2215 Ty->isPromotableIntegerType()) 2216 return ABIArgInfo::getExtend(); 2217 } 2218 2219 break; 2220 2221 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next 2222 // available SSE register is used, the registers are taken in the 2223 // order from %xmm0 to %xmm7. 2224 case SSE: { 2225 llvm::Type *IRType = CGT.ConvertType(Ty); 2226 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0); 2227 ++neededSSE; 2228 break; 2229 } 2230 } 2231 2232 llvm::Type *HighPart = 0; 2233 switch (Hi) { 2234 // Memory was handled previously, ComplexX87 and X87 should 2235 // never occur as hi classes, and X87Up must be preceded by X87, 2236 // which is passed in memory. 2237 case Memory: 2238 case X87: 2239 case ComplexX87: 2240 llvm_unreachable("Invalid classification for hi word."); 2241 2242 case NoClass: break; 2243 2244 case Integer: 2245 ++neededInt; 2246 // Pick an 8-byte type based on the preferred type. 2247 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8); 2248 2249 if (Lo == NoClass) // Pass HighPart at offset 8 in memory. 2250 return ABIArgInfo::getDirect(HighPart, 8); 2251 break; 2252 2253 // X87Up generally doesn't occur here (long double is passed in 2254 // memory), except in situations involving unions. 2255 case X87Up: 2256 case SSE: 2257 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8); 2258 2259 if (Lo == NoClass) // Pass HighPart at offset 8 in memory. 2260 return ABIArgInfo::getDirect(HighPart, 8); 2261 2262 ++neededSSE; 2263 break; 2264 2265 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the 2266 // eightbyte is passed in the upper half of the last used SSE 2267 // register. This only happens when 128-bit vectors are passed. 2268 case SSEUp: 2269 assert(Lo == SSE && "Unexpected SSEUp classification"); 2270 ResType = GetByteVectorType(Ty); 2271 break; 2272 } 2273 2274 // If a high part was specified, merge it together with the low part. It is 2275 // known to pass in the high eightbyte of the result. We do this by forming a 2276 // first class struct aggregate with the high and low part: {low, high} 2277 if (HighPart) 2278 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout()); 2279 2280 return ABIArgInfo::getDirect(ResType); 2281 } 2282 2283 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2284 2285 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 2286 2287 // Keep track of the number of assigned registers. 2288 unsigned freeIntRegs = 6, freeSSERegs = 8; 2289 2290 // If the return value is indirect, then the hidden argument is consuming one 2291 // integer register. 2292 if (FI.getReturnInfo().isIndirect()) 2293 --freeIntRegs; 2294 2295 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers 2296 // get assigned (in left-to-right order) for passing as follows... 2297 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2298 it != ie; ++it) { 2299 unsigned neededInt, neededSSE; 2300 it->info = classifyArgumentType(it->type, freeIntRegs, neededInt, 2301 neededSSE); 2302 2303 // AMD64-ABI 3.2.3p3: If there are no registers available for any 2304 // eightbyte of an argument, the whole argument is passed on the 2305 // stack. If registers have already been assigned for some 2306 // eightbytes of such an argument, the assignments get reverted. 2307 if (freeIntRegs >= neededInt && freeSSERegs >= neededSSE) { 2308 freeIntRegs -= neededInt; 2309 freeSSERegs -= neededSSE; 2310 } else { 2311 it->info = getIndirectResult(it->type, freeIntRegs); 2312 } 2313 } 2314 } 2315 2316 static llvm::Value *EmitVAArgFromMemory(llvm::Value *VAListAddr, 2317 QualType Ty, 2318 CodeGenFunction &CGF) { 2319 llvm::Value *overflow_arg_area_p = 2320 CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p"); 2321 llvm::Value *overflow_arg_area = 2322 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area"); 2323 2324 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16 2325 // byte boundary if alignment needed by type exceeds 8 byte boundary. 2326 // It isn't stated explicitly in the standard, but in practice we use 2327 // alignment greater than 16 where necessary. 2328 uint64_t Align = CGF.getContext().getTypeAlign(Ty) / 8; 2329 if (Align > 8) { 2330 // overflow_arg_area = (overflow_arg_area + align - 1) & -align; 2331 llvm::Value *Offset = 2332 llvm::ConstantInt::get(CGF.Int64Ty, Align - 1); 2333 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset); 2334 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area, 2335 CGF.Int64Ty); 2336 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, -(uint64_t)Align); 2337 overflow_arg_area = 2338 CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), 2339 overflow_arg_area->getType(), 2340 "overflow_arg_area.align"); 2341 } 2342 2343 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area. 2344 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty); 2345 llvm::Value *Res = 2346 CGF.Builder.CreateBitCast(overflow_arg_area, 2347 llvm::PointerType::getUnqual(LTy)); 2348 2349 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to: 2350 // l->overflow_arg_area + sizeof(type). 2351 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to 2352 // an 8 byte boundary. 2353 2354 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8; 2355 llvm::Value *Offset = 2356 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7); 2357 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset, 2358 "overflow_arg_area.next"); 2359 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p); 2360 2361 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type. 2362 return Res; 2363 } 2364 2365 llvm::Value *X86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2366 CodeGenFunction &CGF) const { 2367 // Assume that va_list type is correct; should be pointer to LLVM type: 2368 // struct { 2369 // i32 gp_offset; 2370 // i32 fp_offset; 2371 // i8* overflow_arg_area; 2372 // i8* reg_save_area; 2373 // }; 2374 unsigned neededInt, neededSSE; 2375 2376 Ty = CGF.getContext().getCanonicalType(Ty); 2377 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE); 2378 2379 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed 2380 // in the registers. If not go to step 7. 2381 if (!neededInt && !neededSSE) 2382 return EmitVAArgFromMemory(VAListAddr, Ty, CGF); 2383 2384 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of 2385 // general purpose registers needed to pass type and num_fp to hold 2386 // the number of floating point registers needed. 2387 2388 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into 2389 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or 2390 // l->fp_offset > 304 - num_fp * 16 go to step 7. 2391 // 2392 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of 2393 // register save space). 2394 2395 llvm::Value *InRegs = 0; 2396 llvm::Value *gp_offset_p = 0, *gp_offset = 0; 2397 llvm::Value *fp_offset_p = 0, *fp_offset = 0; 2398 if (neededInt) { 2399 gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p"); 2400 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset"); 2401 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8); 2402 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp"); 2403 } 2404 2405 if (neededSSE) { 2406 fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p"); 2407 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset"); 2408 llvm::Value *FitsInFP = 2409 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16); 2410 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp"); 2411 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP; 2412 } 2413 2414 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 2415 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem"); 2416 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 2417 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock); 2418 2419 // Emit code to load the value if it was passed in registers. 2420 2421 CGF.EmitBlock(InRegBlock); 2422 2423 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with 2424 // an offset of l->gp_offset and/or l->fp_offset. This may require 2425 // copying to a temporary location in case the parameter is passed 2426 // in different register classes or requires an alignment greater 2427 // than 8 for general purpose registers and 16 for XMM registers. 2428 // 2429 // FIXME: This really results in shameful code when we end up needing to 2430 // collect arguments from different places; often what should result in a 2431 // simple assembling of a structure from scattered addresses has many more 2432 // loads than necessary. Can we clean this up? 2433 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty); 2434 llvm::Value *RegAddr = 2435 CGF.Builder.CreateLoad(CGF.Builder.CreateStructGEP(VAListAddr, 3), 2436 "reg_save_area"); 2437 if (neededInt && neededSSE) { 2438 // FIXME: Cleanup. 2439 assert(AI.isDirect() && "Unexpected ABI info for mixed regs"); 2440 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType()); 2441 llvm::Value *Tmp = CGF.CreateTempAlloca(ST); 2442 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs"); 2443 llvm::Type *TyLo = ST->getElementType(0); 2444 llvm::Type *TyHi = ST->getElementType(1); 2445 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) && 2446 "Unexpected ABI info for mixed regs"); 2447 llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo); 2448 llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi); 2449 llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset); 2450 llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2451 llvm::Value *RegLoAddr = TyLo->isFloatingPointTy() ? FPAddr : GPAddr; 2452 llvm::Value *RegHiAddr = TyLo->isFloatingPointTy() ? GPAddr : FPAddr; 2453 llvm::Value *V = 2454 CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegLoAddr, PTyLo)); 2455 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 2456 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegHiAddr, PTyHi)); 2457 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 2458 2459 RegAddr = CGF.Builder.CreateBitCast(Tmp, 2460 llvm::PointerType::getUnqual(LTy)); 2461 } else if (neededInt) { 2462 RegAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset); 2463 RegAddr = CGF.Builder.CreateBitCast(RegAddr, 2464 llvm::PointerType::getUnqual(LTy)); 2465 } else if (neededSSE == 1) { 2466 RegAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2467 RegAddr = CGF.Builder.CreateBitCast(RegAddr, 2468 llvm::PointerType::getUnqual(LTy)); 2469 } else { 2470 assert(neededSSE == 2 && "Invalid number of needed registers!"); 2471 // SSE registers are spaced 16 bytes apart in the register save 2472 // area, we need to collect the two eightbytes together. 2473 llvm::Value *RegAddrLo = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2474 llvm::Value *RegAddrHi = CGF.Builder.CreateConstGEP1_32(RegAddrLo, 16); 2475 llvm::Type *DoubleTy = CGF.DoubleTy; 2476 llvm::Type *DblPtrTy = 2477 llvm::PointerType::getUnqual(DoubleTy); 2478 llvm::StructType *ST = llvm::StructType::get(DoubleTy, 2479 DoubleTy, NULL); 2480 llvm::Value *V, *Tmp = CGF.CreateTempAlloca(ST); 2481 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrLo, 2482 DblPtrTy)); 2483 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 2484 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrHi, 2485 DblPtrTy)); 2486 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 2487 RegAddr = CGF.Builder.CreateBitCast(Tmp, 2488 llvm::PointerType::getUnqual(LTy)); 2489 } 2490 2491 // AMD64-ABI 3.5.7p5: Step 5. Set: 2492 // l->gp_offset = l->gp_offset + num_gp * 8 2493 // l->fp_offset = l->fp_offset + num_fp * 16. 2494 if (neededInt) { 2495 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8); 2496 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset), 2497 gp_offset_p); 2498 } 2499 if (neededSSE) { 2500 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16); 2501 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset), 2502 fp_offset_p); 2503 } 2504 CGF.EmitBranch(ContBlock); 2505 2506 // Emit code to load the value if it was passed in memory. 2507 2508 CGF.EmitBlock(InMemBlock); 2509 llvm::Value *MemAddr = EmitVAArgFromMemory(VAListAddr, Ty, CGF); 2510 2511 // Return the appropriate result. 2512 2513 CGF.EmitBlock(ContBlock); 2514 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(RegAddr->getType(), 2, 2515 "vaarg.addr"); 2516 ResAddr->addIncoming(RegAddr, InRegBlock); 2517 ResAddr->addIncoming(MemAddr, InMemBlock); 2518 return ResAddr; 2519 } 2520 2521 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty) const { 2522 2523 if (Ty->isVoidType()) 2524 return ABIArgInfo::getIgnore(); 2525 2526 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2527 Ty = EnumTy->getDecl()->getIntegerType(); 2528 2529 uint64_t Size = getContext().getTypeSize(Ty); 2530 2531 if (const RecordType *RT = Ty->getAs<RecordType>()) { 2532 if (hasNonTrivialDestructorOrCopyConstructor(RT) || 2533 RT->getDecl()->hasFlexibleArrayMember()) 2534 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 2535 2536 // FIXME: mingw-w64-gcc emits 128-bit struct as i128 2537 if (Size == 128 && 2538 getContext().getTargetInfo().getTriple().getOS() 2539 == llvm::Triple::MinGW32) 2540 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 2541 Size)); 2542 2543 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is 2544 // not 1, 2, 4, or 8 bytes, must be passed by reference." 2545 if (Size <= 64 && 2546 (Size & (Size - 1)) == 0) 2547 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 2548 Size)); 2549 2550 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 2551 } 2552 2553 if (Ty->isPromotableIntegerType()) 2554 return ABIArgInfo::getExtend(); 2555 2556 return ABIArgInfo::getDirect(); 2557 } 2558 2559 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2560 2561 QualType RetTy = FI.getReturnType(); 2562 FI.getReturnInfo() = classify(RetTy); 2563 2564 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2565 it != ie; ++it) 2566 it->info = classify(it->type); 2567 } 2568 2569 llvm::Value *WinX86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2570 CodeGenFunction &CGF) const { 2571 llvm::Type *BPP = CGF.Int8PtrPtrTy; 2572 2573 CGBuilderTy &Builder = CGF.Builder; 2574 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 2575 "ap"); 2576 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 2577 llvm::Type *PTy = 2578 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 2579 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 2580 2581 uint64_t Offset = 2582 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 8); 2583 llvm::Value *NextAddr = 2584 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 2585 "ap.next"); 2586 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 2587 2588 return AddrTyped; 2589 } 2590 2591 namespace { 2592 2593 class NaClX86_64ABIInfo : public ABIInfo { 2594 public: 2595 NaClX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 2596 : ABIInfo(CGT), PInfo(CGT), NInfo(CGT, HasAVX) {} 2597 virtual void computeInfo(CGFunctionInfo &FI) const; 2598 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2599 CodeGenFunction &CGF) const; 2600 private: 2601 PNaClABIInfo PInfo; // Used for generating calls with pnaclcall callingconv. 2602 X86_64ABIInfo NInfo; // Used for everything else. 2603 }; 2604 2605 class NaClX86_64TargetCodeGenInfo : public TargetCodeGenInfo { 2606 public: 2607 NaClX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 2608 : TargetCodeGenInfo(new NaClX86_64ABIInfo(CGT, HasAVX)) {} 2609 }; 2610 2611 } 2612 2613 void NaClX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2614 if (FI.getASTCallingConvention() == CC_PnaclCall) 2615 PInfo.computeInfo(FI); 2616 else 2617 NInfo.computeInfo(FI); 2618 } 2619 2620 llvm::Value *NaClX86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2621 CodeGenFunction &CGF) const { 2622 // Always use the native convention; calling pnacl-style varargs functions 2623 // is unuspported. 2624 return NInfo.EmitVAArg(VAListAddr, Ty, CGF); 2625 } 2626 2627 2628 // PowerPC-32 2629 2630 namespace { 2631 class PPC32TargetCodeGenInfo : public DefaultTargetCodeGenInfo { 2632 public: 2633 PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {} 2634 2635 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2636 // This is recovered from gcc output. 2637 return 1; // r1 is the dedicated stack pointer 2638 } 2639 2640 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2641 llvm::Value *Address) const; 2642 }; 2643 2644 } 2645 2646 bool 2647 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2648 llvm::Value *Address) const { 2649 // This is calculated from the LLVM and GCC tables and verified 2650 // against gcc output. AFAIK all ABIs use the same encoding. 2651 2652 CodeGen::CGBuilderTy &Builder = CGF.Builder; 2653 2654 llvm::IntegerType *i8 = CGF.Int8Ty; 2655 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 2656 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 2657 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16); 2658 2659 // 0-31: r0-31, the 4-byte general-purpose registers 2660 AssignToArrayRange(Builder, Address, Four8, 0, 31); 2661 2662 // 32-63: fp0-31, the 8-byte floating-point registers 2663 AssignToArrayRange(Builder, Address, Eight8, 32, 63); 2664 2665 // 64-76 are various 4-byte special-purpose registers: 2666 // 64: mq 2667 // 65: lr 2668 // 66: ctr 2669 // 67: ap 2670 // 68-75 cr0-7 2671 // 76: xer 2672 AssignToArrayRange(Builder, Address, Four8, 64, 76); 2673 2674 // 77-108: v0-31, the 16-byte vector registers 2675 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108); 2676 2677 // 109: vrsave 2678 // 110: vscr 2679 // 111: spe_acc 2680 // 112: spefscr 2681 // 113: sfp 2682 AssignToArrayRange(Builder, Address, Four8, 109, 113); 2683 2684 return false; 2685 } 2686 2687 // PowerPC-64 2688 2689 namespace { 2690 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information. 2691 class PPC64_SVR4_ABIInfo : public DefaultABIInfo { 2692 2693 public: 2694 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {} 2695 2696 bool isPromotableTypeForABI(QualType Ty) const; 2697 2698 ABIArgInfo classifyReturnType(QualType RetTy) const; 2699 ABIArgInfo classifyArgumentType(QualType Ty) const; 2700 2701 // TODO: We can add more logic to computeInfo to improve performance. 2702 // Example: For aggregate arguments that fit in a register, we could 2703 // use getDirectInReg (as is done below for structs containing a single 2704 // floating-point value) to avoid pushing them to memory on function 2705 // entry. This would require changing the logic in PPCISelLowering 2706 // when lowering the parameters in the caller and args in the callee. 2707 virtual void computeInfo(CGFunctionInfo &FI) const { 2708 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 2709 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2710 it != ie; ++it) { 2711 // We rely on the default argument classification for the most part. 2712 // One exception: An aggregate containing a single floating-point 2713 // item must be passed in a register if one is available. 2714 const Type *T = isSingleElementStruct(it->type, getContext()); 2715 if (T) { 2716 const BuiltinType *BT = T->getAs<BuiltinType>(); 2717 if (BT && BT->isFloatingPoint()) { 2718 QualType QT(T, 0); 2719 it->info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT)); 2720 continue; 2721 } 2722 } 2723 it->info = classifyArgumentType(it->type); 2724 } 2725 } 2726 2727 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, 2728 QualType Ty, 2729 CodeGenFunction &CGF) const; 2730 }; 2731 2732 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo { 2733 public: 2734 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT) 2735 : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT)) {} 2736 2737 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2738 // This is recovered from gcc output. 2739 return 1; // r1 is the dedicated stack pointer 2740 } 2741 2742 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2743 llvm::Value *Address) const; 2744 }; 2745 2746 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo { 2747 public: 2748 PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {} 2749 2750 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2751 // This is recovered from gcc output. 2752 return 1; // r1 is the dedicated stack pointer 2753 } 2754 2755 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2756 llvm::Value *Address) const; 2757 }; 2758 2759 } 2760 2761 // Return true if the ABI requires Ty to be passed sign- or zero- 2762 // extended to 64 bits. 2763 bool 2764 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const { 2765 // Treat an enum type as its underlying type. 2766 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2767 Ty = EnumTy->getDecl()->getIntegerType(); 2768 2769 // Promotable integer types are required to be promoted by the ABI. 2770 if (Ty->isPromotableIntegerType()) 2771 return true; 2772 2773 // In addition to the usual promotable integer types, we also need to 2774 // extend all 32-bit types, since the ABI requires promotion to 64 bits. 2775 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 2776 switch (BT->getKind()) { 2777 case BuiltinType::Int: 2778 case BuiltinType::UInt: 2779 return true; 2780 default: 2781 break; 2782 } 2783 2784 return false; 2785 } 2786 2787 ABIArgInfo 2788 PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const { 2789 if (Ty->isAnyComplexType()) 2790 return ABIArgInfo::getDirect(); 2791 2792 if (isAggregateTypeForABI(Ty)) { 2793 // Records with non trivial destructors/constructors should not be passed 2794 // by value. 2795 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 2796 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 2797 2798 return ABIArgInfo::getIndirect(0); 2799 } 2800 2801 return (isPromotableTypeForABI(Ty) ? 2802 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 2803 } 2804 2805 ABIArgInfo 2806 PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const { 2807 if (RetTy->isVoidType()) 2808 return ABIArgInfo::getIgnore(); 2809 2810 if (RetTy->isAnyComplexType()) 2811 return ABIArgInfo::getDirect(); 2812 2813 if (isAggregateTypeForABI(RetTy)) 2814 return ABIArgInfo::getIndirect(0); 2815 2816 return (isPromotableTypeForABI(RetTy) ? 2817 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 2818 } 2819 2820 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine. 2821 llvm::Value *PPC64_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr, 2822 QualType Ty, 2823 CodeGenFunction &CGF) const { 2824 llvm::Type *BP = CGF.Int8PtrTy; 2825 llvm::Type *BPP = CGF.Int8PtrPtrTy; 2826 2827 CGBuilderTy &Builder = CGF.Builder; 2828 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 2829 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 2830 2831 // Update the va_list pointer. The pointer should be bumped by the 2832 // size of the object. We can trust getTypeSize() except for a complex 2833 // type whose base type is smaller than a doubleword. For these, the 2834 // size of the object is 16 bytes; see below for further explanation. 2835 unsigned SizeInBytes = CGF.getContext().getTypeSize(Ty) / 8; 2836 QualType BaseTy; 2837 unsigned CplxBaseSize = 0; 2838 2839 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) { 2840 BaseTy = CTy->getElementType(); 2841 CplxBaseSize = CGF.getContext().getTypeSize(BaseTy) / 8; 2842 if (CplxBaseSize < 8) 2843 SizeInBytes = 16; 2844 } 2845 2846 unsigned Offset = llvm::RoundUpToAlignment(SizeInBytes, 8); 2847 llvm::Value *NextAddr = 2848 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int64Ty, Offset), 2849 "ap.next"); 2850 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 2851 2852 // If we have a complex type and the base type is smaller than 8 bytes, 2853 // the ABI calls for the real and imaginary parts to be right-adjusted 2854 // in separate doublewords. However, Clang expects us to produce a 2855 // pointer to a structure with the two parts packed tightly. So generate 2856 // loads of the real and imaginary parts relative to the va_list pointer, 2857 // and store them to a temporary structure. 2858 if (CplxBaseSize && CplxBaseSize < 8) { 2859 llvm::Value *RealAddr = Builder.CreatePtrToInt(Addr, CGF.Int64Ty); 2860 llvm::Value *ImagAddr = RealAddr; 2861 RealAddr = Builder.CreateAdd(RealAddr, Builder.getInt64(8 - CplxBaseSize)); 2862 ImagAddr = Builder.CreateAdd(ImagAddr, Builder.getInt64(16 - CplxBaseSize)); 2863 llvm::Type *PBaseTy = llvm::PointerType::getUnqual(CGF.ConvertType(BaseTy)); 2864 RealAddr = Builder.CreateIntToPtr(RealAddr, PBaseTy); 2865 ImagAddr = Builder.CreateIntToPtr(ImagAddr, PBaseTy); 2866 llvm::Value *Real = Builder.CreateLoad(RealAddr, false, ".vareal"); 2867 llvm::Value *Imag = Builder.CreateLoad(ImagAddr, false, ".vaimag"); 2868 llvm::Value *Ptr = CGF.CreateTempAlloca(CGT.ConvertTypeForMem(Ty), 2869 "vacplx"); 2870 llvm::Value *RealPtr = Builder.CreateStructGEP(Ptr, 0, ".real"); 2871 llvm::Value *ImagPtr = Builder.CreateStructGEP(Ptr, 1, ".imag"); 2872 Builder.CreateStore(Real, RealPtr, false); 2873 Builder.CreateStore(Imag, ImagPtr, false); 2874 return Ptr; 2875 } 2876 2877 // If the argument is smaller than 8 bytes, it is right-adjusted in 2878 // its doubleword slot. Adjust the pointer to pick it up from the 2879 // correct offset. 2880 if (SizeInBytes < 8) { 2881 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty); 2882 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt64(8 - SizeInBytes)); 2883 Addr = Builder.CreateIntToPtr(AddrAsInt, BP); 2884 } 2885 2886 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 2887 return Builder.CreateBitCast(Addr, PTy); 2888 } 2889 2890 static bool 2891 PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2892 llvm::Value *Address) { 2893 // This is calculated from the LLVM and GCC tables and verified 2894 // against gcc output. AFAIK all ABIs use the same encoding. 2895 2896 CodeGen::CGBuilderTy &Builder = CGF.Builder; 2897 2898 llvm::IntegerType *i8 = CGF.Int8Ty; 2899 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 2900 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 2901 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16); 2902 2903 // 0-31: r0-31, the 8-byte general-purpose registers 2904 AssignToArrayRange(Builder, Address, Eight8, 0, 31); 2905 2906 // 32-63: fp0-31, the 8-byte floating-point registers 2907 AssignToArrayRange(Builder, Address, Eight8, 32, 63); 2908 2909 // 64-76 are various 4-byte special-purpose registers: 2910 // 64: mq 2911 // 65: lr 2912 // 66: ctr 2913 // 67: ap 2914 // 68-75 cr0-7 2915 // 76: xer 2916 AssignToArrayRange(Builder, Address, Four8, 64, 76); 2917 2918 // 77-108: v0-31, the 16-byte vector registers 2919 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108); 2920 2921 // 109: vrsave 2922 // 110: vscr 2923 // 111: spe_acc 2924 // 112: spefscr 2925 // 113: sfp 2926 AssignToArrayRange(Builder, Address, Four8, 109, 113); 2927 2928 return false; 2929 } 2930 2931 bool 2932 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable( 2933 CodeGen::CodeGenFunction &CGF, 2934 llvm::Value *Address) const { 2935 2936 return PPC64_initDwarfEHRegSizeTable(CGF, Address); 2937 } 2938 2939 bool 2940 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2941 llvm::Value *Address) const { 2942 2943 return PPC64_initDwarfEHRegSizeTable(CGF, Address); 2944 } 2945 2946 //===----------------------------------------------------------------------===// 2947 // ARM ABI Implementation 2948 //===----------------------------------------------------------------------===// 2949 2950 namespace { 2951 2952 class ARMABIInfo : public ABIInfo { 2953 public: 2954 enum ABIKind { 2955 APCS = 0, 2956 AAPCS = 1, 2957 AAPCS_VFP 2958 }; 2959 2960 private: 2961 ABIKind Kind; 2962 2963 public: 2964 ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind) : ABIInfo(CGT), Kind(_Kind) { 2965 setRuntimeCC(); 2966 } 2967 2968 bool isEABI() const { 2969 StringRef Env = 2970 getContext().getTargetInfo().getTriple().getEnvironmentName(); 2971 return (Env == "gnueabi" || Env == "eabi" || 2972 Env == "android" || Env == "androideabi"); 2973 } 2974 2975 private: 2976 ABIKind getABIKind() const { return Kind; } 2977 2978 ABIArgInfo classifyReturnType(QualType RetTy) const; 2979 ABIArgInfo classifyArgumentType(QualType RetTy, int *VFPRegs, 2980 unsigned &AllocatedVFP, 2981 bool &IsHA) const; 2982 bool isIllegalVectorType(QualType Ty) const; 2983 2984 virtual void computeInfo(CGFunctionInfo &FI) const; 2985 2986 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2987 CodeGenFunction &CGF) const; 2988 2989 llvm::CallingConv::ID getLLVMDefaultCC() const; 2990 llvm::CallingConv::ID getABIDefaultCC() const; 2991 void setRuntimeCC(); 2992 }; 2993 2994 class ARMTargetCodeGenInfo : public TargetCodeGenInfo { 2995 public: 2996 ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K) 2997 :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {} 2998 2999 const ARMABIInfo &getABIInfo() const { 3000 return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo()); 3001 } 3002 3003 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 3004 return 13; 3005 } 3006 3007 StringRef getARCRetainAutoreleasedReturnValueMarker() const { 3008 return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue"; 3009 } 3010 3011 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 3012 llvm::Value *Address) const { 3013 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 3014 3015 // 0-15 are the 16 integer registers. 3016 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15); 3017 return false; 3018 } 3019 3020 unsigned getSizeOfUnwindException() const { 3021 if (getABIInfo().isEABI()) return 88; 3022 return TargetCodeGenInfo::getSizeOfUnwindException(); 3023 } 3024 }; 3025 3026 } 3027 3028 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const { 3029 // To correctly handle Homogeneous Aggregate, we need to keep track of the 3030 // VFP registers allocated so far. 3031 // C.1.vfp If the argument is a VFP CPRC and there are sufficient consecutive 3032 // VFP registers of the appropriate type unallocated then the argument is 3033 // allocated to the lowest-numbered sequence of such registers. 3034 // C.2.vfp If the argument is a VFP CPRC then any VFP registers that are 3035 // unallocated are marked as unavailable. 3036 unsigned AllocatedVFP = 0; 3037 int VFPRegs[16] = { 0 }; 3038 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 3039 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 3040 it != ie; ++it) { 3041 unsigned PreAllocation = AllocatedVFP; 3042 bool IsHA = false; 3043 // 6.1.2.3 There is one VFP co-processor register class using registers 3044 // s0-s15 (d0-d7) for passing arguments. 3045 const unsigned NumVFPs = 16; 3046 it->info = classifyArgumentType(it->type, VFPRegs, AllocatedVFP, IsHA); 3047 // If we do not have enough VFP registers for the HA, any VFP registers 3048 // that are unallocated are marked as unavailable. To achieve this, we add 3049 // padding of (NumVFPs - PreAllocation) floats. 3050 if (IsHA && AllocatedVFP > NumVFPs && PreAllocation < NumVFPs) { 3051 llvm::Type *PaddingTy = llvm::ArrayType::get( 3052 llvm::Type::getFloatTy(getVMContext()), NumVFPs - PreAllocation); 3053 it->info = ABIArgInfo::getExpandWithPadding(false, PaddingTy); 3054 } 3055 } 3056 3057 // Always honor user-specified calling convention. 3058 if (FI.getCallingConvention() != llvm::CallingConv::C) 3059 return; 3060 3061 llvm::CallingConv::ID cc = getRuntimeCC(); 3062 if (cc != llvm::CallingConv::C) 3063 FI.setEffectiveCallingConvention(cc); 3064 } 3065 3066 /// Return the default calling convention that LLVM will use. 3067 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const { 3068 // The default calling convention that LLVM will infer. 3069 if (getContext().getTargetInfo().getTriple().getEnvironmentName()=="gnueabihf") 3070 return llvm::CallingConv::ARM_AAPCS_VFP; 3071 else if (isEABI()) 3072 return llvm::CallingConv::ARM_AAPCS; 3073 else 3074 return llvm::CallingConv::ARM_APCS; 3075 } 3076 3077 /// Return the calling convention that our ABI would like us to use 3078 /// as the C calling convention. 3079 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const { 3080 switch (getABIKind()) { 3081 case APCS: return llvm::CallingConv::ARM_APCS; 3082 case AAPCS: return llvm::CallingConv::ARM_AAPCS; 3083 case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP; 3084 } 3085 llvm_unreachable("bad ABI kind"); 3086 } 3087 3088 void ARMABIInfo::setRuntimeCC() { 3089 assert(getRuntimeCC() == llvm::CallingConv::C); 3090 3091 // Don't muddy up the IR with a ton of explicit annotations if 3092 // they'd just match what LLVM will infer from the triple. 3093 llvm::CallingConv::ID abiCC = getABIDefaultCC(); 3094 if (abiCC != getLLVMDefaultCC()) 3095 RuntimeCC = abiCC; 3096 } 3097 3098 /// isHomogeneousAggregate - Return true if a type is an AAPCS-VFP homogeneous 3099 /// aggregate. If HAMembers is non-null, the number of base elements 3100 /// contained in the type is returned through it; this is used for the 3101 /// recursive calls that check aggregate component types. 3102 static bool isHomogeneousAggregate(QualType Ty, const Type *&Base, 3103 ASTContext &Context, 3104 uint64_t *HAMembers = 0) { 3105 uint64_t Members = 0; 3106 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) { 3107 if (!isHomogeneousAggregate(AT->getElementType(), Base, Context, &Members)) 3108 return false; 3109 Members *= AT->getSize().getZExtValue(); 3110 } else if (const RecordType *RT = Ty->getAs<RecordType>()) { 3111 const RecordDecl *RD = RT->getDecl(); 3112 if (RD->hasFlexibleArrayMember()) 3113 return false; 3114 3115 Members = 0; 3116 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 3117 i != e; ++i) { 3118 const FieldDecl *FD = *i; 3119 uint64_t FldMembers; 3120 if (!isHomogeneousAggregate(FD->getType(), Base, Context, &FldMembers)) 3121 return false; 3122 3123 Members = (RD->isUnion() ? 3124 std::max(Members, FldMembers) : Members + FldMembers); 3125 } 3126 } else { 3127 Members = 1; 3128 if (const ComplexType *CT = Ty->getAs<ComplexType>()) { 3129 Members = 2; 3130 Ty = CT->getElementType(); 3131 } 3132 3133 // Homogeneous aggregates for AAPCS-VFP must have base types of float, 3134 // double, or 64-bit or 128-bit vectors. 3135 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 3136 if (BT->getKind() != BuiltinType::Float && 3137 BT->getKind() != BuiltinType::Double && 3138 BT->getKind() != BuiltinType::LongDouble) 3139 return false; 3140 } else if (const VectorType *VT = Ty->getAs<VectorType>()) { 3141 unsigned VecSize = Context.getTypeSize(VT); 3142 if (VecSize != 64 && VecSize != 128) 3143 return false; 3144 } else { 3145 return false; 3146 } 3147 3148 // The base type must be the same for all members. Vector types of the 3149 // same total size are treated as being equivalent here. 3150 const Type *TyPtr = Ty.getTypePtr(); 3151 if (!Base) 3152 Base = TyPtr; 3153 if (Base != TyPtr && 3154 (!Base->isVectorType() || !TyPtr->isVectorType() || 3155 Context.getTypeSize(Base) != Context.getTypeSize(TyPtr))) 3156 return false; 3157 } 3158 3159 // Homogeneous Aggregates can have at most 4 members of the base type. 3160 if (HAMembers) 3161 *HAMembers = Members; 3162 3163 return (Members > 0 && Members <= 4); 3164 } 3165 3166 /// markAllocatedVFPs - update VFPRegs according to the alignment and 3167 /// number of VFP registers (unit is S register) requested. 3168 static void markAllocatedVFPs(int *VFPRegs, unsigned &AllocatedVFP, 3169 unsigned Alignment, 3170 unsigned NumRequired) { 3171 // Early Exit. 3172 if (AllocatedVFP >= 16) 3173 return; 3174 // C.1.vfp If the argument is a VFP CPRC and there are sufficient consecutive 3175 // VFP registers of the appropriate type unallocated then the argument is 3176 // allocated to the lowest-numbered sequence of such registers. 3177 for (unsigned I = 0; I < 16; I += Alignment) { 3178 bool FoundSlot = true; 3179 for (unsigned J = I, JEnd = I + NumRequired; J < JEnd; J++) 3180 if (J >= 16 || VFPRegs[J]) { 3181 FoundSlot = false; 3182 break; 3183 } 3184 if (FoundSlot) { 3185 for (unsigned J = I, JEnd = I + NumRequired; J < JEnd; J++) 3186 VFPRegs[J] = 1; 3187 AllocatedVFP += NumRequired; 3188 return; 3189 } 3190 } 3191 // C.2.vfp If the argument is a VFP CPRC then any VFP registers that are 3192 // unallocated are marked as unavailable. 3193 for (unsigned I = 0; I < 16; I++) 3194 VFPRegs[I] = 1; 3195 AllocatedVFP = 17; // We do not have enough VFP registers. 3196 } 3197 3198 ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, int *VFPRegs, 3199 unsigned &AllocatedVFP, 3200 bool &IsHA) const { 3201 // We update number of allocated VFPs according to 3202 // 6.1.2.1 The following argument types are VFP CPRCs: 3203 // A single-precision floating-point type (including promoted 3204 // half-precision types); A double-precision floating-point type; 3205 // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate 3206 // with a Base Type of a single- or double-precision floating-point type, 3207 // 64-bit containerized vectors or 128-bit containerized vectors with one 3208 // to four Elements. 3209 3210 // Handle illegal vector types here. 3211 if (isIllegalVectorType(Ty)) { 3212 uint64_t Size = getContext().getTypeSize(Ty); 3213 if (Size <= 32) { 3214 llvm::Type *ResType = 3215 llvm::Type::getInt32Ty(getVMContext()); 3216 return ABIArgInfo::getDirect(ResType); 3217 } 3218 if (Size == 64) { 3219 llvm::Type *ResType = llvm::VectorType::get( 3220 llvm::Type::getInt32Ty(getVMContext()), 2); 3221 markAllocatedVFPs(VFPRegs, AllocatedVFP, 2, 2); 3222 return ABIArgInfo::getDirect(ResType); 3223 } 3224 if (Size == 128) { 3225 llvm::Type *ResType = llvm::VectorType::get( 3226 llvm::Type::getInt32Ty(getVMContext()), 4); 3227 markAllocatedVFPs(VFPRegs, AllocatedVFP, 4, 4); 3228 return ABIArgInfo::getDirect(ResType); 3229 } 3230 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3231 } 3232 // Update VFPRegs for legal vector types. 3233 if (const VectorType *VT = Ty->getAs<VectorType>()) { 3234 uint64_t Size = getContext().getTypeSize(VT); 3235 // Size of a legal vector should be power of 2 and above 64. 3236 markAllocatedVFPs(VFPRegs, AllocatedVFP, Size >= 128 ? 4 : 2, Size / 32); 3237 } 3238 // Update VFPRegs for floating point types. 3239 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 3240 if (BT->getKind() == BuiltinType::Half || 3241 BT->getKind() == BuiltinType::Float) 3242 markAllocatedVFPs(VFPRegs, AllocatedVFP, 1, 1); 3243 if (BT->getKind() == BuiltinType::Double || 3244 BT->getKind() == BuiltinType::LongDouble) 3245 markAllocatedVFPs(VFPRegs, AllocatedVFP, 2, 2); 3246 } 3247 3248 if (!isAggregateTypeForABI(Ty)) { 3249 // Treat an enum type as its underlying type. 3250 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 3251 Ty = EnumTy->getDecl()->getIntegerType(); 3252 3253 return (Ty->isPromotableIntegerType() ? 3254 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3255 } 3256 3257 // Ignore empty records. 3258 if (isEmptyRecord(getContext(), Ty, true)) 3259 return ABIArgInfo::getIgnore(); 3260 3261 // Structures with either a non-trivial destructor or a non-trivial 3262 // copy constructor are always indirect. 3263 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 3264 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3265 3266 if (getABIKind() == ARMABIInfo::AAPCS_VFP) { 3267 // Homogeneous Aggregates need to be expanded when we can fit the aggregate 3268 // into VFP registers. 3269 const Type *Base = 0; 3270 uint64_t Members = 0; 3271 if (isHomogeneousAggregate(Ty, Base, getContext(), &Members)) { 3272 assert(Base && "Base class should be set for homogeneous aggregate"); 3273 // Base can be a floating-point or a vector. 3274 if (Base->isVectorType()) { 3275 // ElementSize is in number of floats. 3276 unsigned ElementSize = getContext().getTypeSize(Base) == 64 ? 2 : 4; 3277 markAllocatedVFPs(VFPRegs, AllocatedVFP, ElementSize, 3278 Members * ElementSize); 3279 } else if (Base->isSpecificBuiltinType(BuiltinType::Float)) 3280 markAllocatedVFPs(VFPRegs, AllocatedVFP, 1, Members); 3281 else { 3282 assert(Base->isSpecificBuiltinType(BuiltinType::Double) || 3283 Base->isSpecificBuiltinType(BuiltinType::LongDouble)); 3284 markAllocatedVFPs(VFPRegs, AllocatedVFP, 2, Members * 2); 3285 } 3286 IsHA = true; 3287 return ABIArgInfo::getExpand(); 3288 } 3289 } 3290 3291 // Support byval for ARM. 3292 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at 3293 // most 8-byte. We realign the indirect argument if type alignment is bigger 3294 // than ABI alignment. 3295 uint64_t ABIAlign = 4; 3296 uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8; 3297 if (getABIKind() == ARMABIInfo::AAPCS_VFP || 3298 getABIKind() == ARMABIInfo::AAPCS) 3299 ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8); 3300 if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) { 3301 return ABIArgInfo::getIndirect(0, /*ByVal=*/true, 3302 /*Realign=*/TyAlign > ABIAlign); 3303 } 3304 3305 // Otherwise, pass by coercing to a structure of the appropriate size. 3306 llvm::Type* ElemTy; 3307 unsigned SizeRegs; 3308 // FIXME: Try to match the types of the arguments more accurately where 3309 // we can. 3310 if (getContext().getTypeAlign(Ty) <= 32) { 3311 ElemTy = llvm::Type::getInt32Ty(getVMContext()); 3312 SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32; 3313 } else { 3314 ElemTy = llvm::Type::getInt64Ty(getVMContext()); 3315 SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64; 3316 } 3317 3318 llvm::Type *STy = 3319 llvm::StructType::get(llvm::ArrayType::get(ElemTy, SizeRegs), NULL); 3320 return ABIArgInfo::getDirect(STy); 3321 } 3322 3323 static bool isIntegerLikeType(QualType Ty, ASTContext &Context, 3324 llvm::LLVMContext &VMContext) { 3325 // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure 3326 // is called integer-like if its size is less than or equal to one word, and 3327 // the offset of each of its addressable sub-fields is zero. 3328 3329 uint64_t Size = Context.getTypeSize(Ty); 3330 3331 // Check that the type fits in a word. 3332 if (Size > 32) 3333 return false; 3334 3335 // FIXME: Handle vector types! 3336 if (Ty->isVectorType()) 3337 return false; 3338 3339 // Float types are never treated as "integer like". 3340 if (Ty->isRealFloatingType()) 3341 return false; 3342 3343 // If this is a builtin or pointer type then it is ok. 3344 if (Ty->getAs<BuiltinType>() || Ty->isPointerType()) 3345 return true; 3346 3347 // Small complex integer types are "integer like". 3348 if (const ComplexType *CT = Ty->getAs<ComplexType>()) 3349 return isIntegerLikeType(CT->getElementType(), Context, VMContext); 3350 3351 // Single element and zero sized arrays should be allowed, by the definition 3352 // above, but they are not. 3353 3354 // Otherwise, it must be a record type. 3355 const RecordType *RT = Ty->getAs<RecordType>(); 3356 if (!RT) return false; 3357 3358 // Ignore records with flexible arrays. 3359 const RecordDecl *RD = RT->getDecl(); 3360 if (RD->hasFlexibleArrayMember()) 3361 return false; 3362 3363 // Check that all sub-fields are at offset 0, and are themselves "integer 3364 // like". 3365 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD); 3366 3367 bool HadField = false; 3368 unsigned idx = 0; 3369 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 3370 i != e; ++i, ++idx) { 3371 const FieldDecl *FD = *i; 3372 3373 // Bit-fields are not addressable, we only need to verify they are "integer 3374 // like". We still have to disallow a subsequent non-bitfield, for example: 3375 // struct { int : 0; int x } 3376 // is non-integer like according to gcc. 3377 if (FD->isBitField()) { 3378 if (!RD->isUnion()) 3379 HadField = true; 3380 3381 if (!isIntegerLikeType(FD->getType(), Context, VMContext)) 3382 return false; 3383 3384 continue; 3385 } 3386 3387 // Check if this field is at offset 0. 3388 if (Layout.getFieldOffset(idx) != 0) 3389 return false; 3390 3391 if (!isIntegerLikeType(FD->getType(), Context, VMContext)) 3392 return false; 3393 3394 // Only allow at most one field in a structure. This doesn't match the 3395 // wording above, but follows gcc in situations with a field following an 3396 // empty structure. 3397 if (!RD->isUnion()) { 3398 if (HadField) 3399 return false; 3400 3401 HadField = true; 3402 } 3403 } 3404 3405 return true; 3406 } 3407 3408 ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy) const { 3409 if (RetTy->isVoidType()) 3410 return ABIArgInfo::getIgnore(); 3411 3412 // Large vector types should be returned via memory. 3413 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) 3414 return ABIArgInfo::getIndirect(0); 3415 3416 if (!isAggregateTypeForABI(RetTy)) { 3417 // Treat an enum type as its underlying type. 3418 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 3419 RetTy = EnumTy->getDecl()->getIntegerType(); 3420 3421 return (RetTy->isPromotableIntegerType() ? 3422 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3423 } 3424 3425 // Structures with either a non-trivial destructor or a non-trivial 3426 // copy constructor are always indirect. 3427 if (isRecordWithNonTrivialDestructorOrCopyConstructor(RetTy)) 3428 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3429 3430 // Are we following APCS? 3431 if (getABIKind() == APCS) { 3432 if (isEmptyRecord(getContext(), RetTy, false)) 3433 return ABIArgInfo::getIgnore(); 3434 3435 // Complex types are all returned as packed integers. 3436 // 3437 // FIXME: Consider using 2 x vector types if the back end handles them 3438 // correctly. 3439 if (RetTy->isAnyComplexType()) 3440 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 3441 getContext().getTypeSize(RetTy))); 3442 3443 // Integer like structures are returned in r0. 3444 if (isIntegerLikeType(RetTy, getContext(), getVMContext())) { 3445 // Return in the smallest viable integer type. 3446 uint64_t Size = getContext().getTypeSize(RetTy); 3447 if (Size <= 8) 3448 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 3449 if (Size <= 16) 3450 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 3451 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 3452 } 3453 3454 // Otherwise return in memory. 3455 return ABIArgInfo::getIndirect(0); 3456 } 3457 3458 // Otherwise this is an AAPCS variant. 3459 3460 if (isEmptyRecord(getContext(), RetTy, true)) 3461 return ABIArgInfo::getIgnore(); 3462 3463 // Check for homogeneous aggregates with AAPCS-VFP. 3464 if (getABIKind() == AAPCS_VFP) { 3465 const Type *Base = 0; 3466 if (isHomogeneousAggregate(RetTy, Base, getContext())) { 3467 assert(Base && "Base class should be set for homogeneous aggregate"); 3468 // Homogeneous Aggregates are returned directly. 3469 return ABIArgInfo::getDirect(); 3470 } 3471 } 3472 3473 // Aggregates <= 4 bytes are returned in r0; other aggregates 3474 // are returned indirectly. 3475 uint64_t Size = getContext().getTypeSize(RetTy); 3476 if (Size <= 32) { 3477 // Return in the smallest viable integer type. 3478 if (Size <= 8) 3479 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 3480 if (Size <= 16) 3481 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 3482 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 3483 } 3484 3485 return ABIArgInfo::getIndirect(0); 3486 } 3487 3488 /// isIllegalVector - check whether Ty is an illegal vector type. 3489 bool ARMABIInfo::isIllegalVectorType(QualType Ty) const { 3490 if (const VectorType *VT = Ty->getAs<VectorType>()) { 3491 // Check whether VT is legal. 3492 unsigned NumElements = VT->getNumElements(); 3493 // NumElements should be power of 2. 3494 if (((NumElements & (NumElements - 1)) != 0) && NumElements != 3) 3495 return true; 3496 } 3497 return false; 3498 } 3499 3500 llvm::Value *ARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3501 CodeGenFunction &CGF) const { 3502 llvm::Type *BP = CGF.Int8PtrTy; 3503 llvm::Type *BPP = CGF.Int8PtrPtrTy; 3504 3505 CGBuilderTy &Builder = CGF.Builder; 3506 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 3507 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 3508 3509 uint64_t Size = CGF.getContext().getTypeSize(Ty) / 8; 3510 uint64_t TyAlign = CGF.getContext().getTypeAlign(Ty) / 8; 3511 bool IsIndirect = false; 3512 3513 // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for 3514 // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte. 3515 if (getABIKind() == ARMABIInfo::AAPCS_VFP || 3516 getABIKind() == ARMABIInfo::AAPCS) 3517 TyAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8); 3518 else 3519 TyAlign = 4; 3520 // Use indirect if size of the illegal vector is bigger than 32 bytes. 3521 if (isIllegalVectorType(Ty) && Size > 32) { 3522 IsIndirect = true; 3523 Size = 4; 3524 TyAlign = 4; 3525 } 3526 3527 // Handle address alignment for ABI alignment > 4 bytes. 3528 if (TyAlign > 4) { 3529 assert((TyAlign & (TyAlign - 1)) == 0 && 3530 "Alignment is not power of 2!"); 3531 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int32Ty); 3532 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt32(TyAlign - 1)); 3533 AddrAsInt = Builder.CreateAnd(AddrAsInt, Builder.getInt32(~(TyAlign - 1))); 3534 Addr = Builder.CreateIntToPtr(AddrAsInt, BP, "ap.align"); 3535 } 3536 3537 uint64_t Offset = 3538 llvm::RoundUpToAlignment(Size, 4); 3539 llvm::Value *NextAddr = 3540 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 3541 "ap.next"); 3542 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 3543 3544 if (IsIndirect) 3545 Addr = Builder.CreateLoad(Builder.CreateBitCast(Addr, BPP)); 3546 else if (TyAlign < CGF.getContext().getTypeAlign(Ty) / 8) { 3547 // We can't directly cast ap.cur to pointer to a vector type, since ap.cur 3548 // may not be correctly aligned for the vector type. We create an aligned 3549 // temporary space and copy the content over from ap.cur to the temporary 3550 // space. This is necessary if the natural alignment of the type is greater 3551 // than the ABI alignment. 3552 llvm::Type *I8PtrTy = Builder.getInt8PtrTy(); 3553 CharUnits CharSize = getContext().getTypeSizeInChars(Ty); 3554 llvm::Value *AlignedTemp = CGF.CreateTempAlloca(CGF.ConvertType(Ty), 3555 "var.align"); 3556 llvm::Value *Dst = Builder.CreateBitCast(AlignedTemp, I8PtrTy); 3557 llvm::Value *Src = Builder.CreateBitCast(Addr, I8PtrTy); 3558 Builder.CreateMemCpy(Dst, Src, 3559 llvm::ConstantInt::get(CGF.IntPtrTy, CharSize.getQuantity()), 3560 TyAlign, false); 3561 Addr = AlignedTemp; //The content is in aligned location. 3562 } 3563 llvm::Type *PTy = 3564 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 3565 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 3566 3567 return AddrTyped; 3568 } 3569 3570 namespace { 3571 3572 class NaClARMABIInfo : public ABIInfo { 3573 public: 3574 NaClARMABIInfo(CodeGen::CodeGenTypes &CGT, ARMABIInfo::ABIKind Kind) 3575 : ABIInfo(CGT), PInfo(CGT), NInfo(CGT, Kind) {} 3576 virtual void computeInfo(CGFunctionInfo &FI) const; 3577 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3578 CodeGenFunction &CGF) const; 3579 private: 3580 PNaClABIInfo PInfo; // Used for generating calls with pnaclcall callingconv. 3581 ARMABIInfo NInfo; // Used for everything else. 3582 }; 3583 3584 class NaClARMTargetCodeGenInfo : public TargetCodeGenInfo { 3585 public: 3586 NaClARMTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, ARMABIInfo::ABIKind Kind) 3587 : TargetCodeGenInfo(new NaClARMABIInfo(CGT, Kind)) {} 3588 }; 3589 3590 } 3591 3592 void NaClARMABIInfo::computeInfo(CGFunctionInfo &FI) const { 3593 if (FI.getASTCallingConvention() == CC_PnaclCall) 3594 PInfo.computeInfo(FI); 3595 else 3596 static_cast<const ABIInfo&>(NInfo).computeInfo(FI); 3597 } 3598 3599 llvm::Value *NaClARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3600 CodeGenFunction &CGF) const { 3601 // Always use the native convention; calling pnacl-style varargs functions 3602 // is unsupported. 3603 return static_cast<const ABIInfo&>(NInfo).EmitVAArg(VAListAddr, Ty, CGF); 3604 } 3605 3606 //===----------------------------------------------------------------------===// 3607 // AArch64 ABI Implementation 3608 //===----------------------------------------------------------------------===// 3609 3610 namespace { 3611 3612 class AArch64ABIInfo : public ABIInfo { 3613 public: 3614 AArch64ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 3615 3616 private: 3617 // The AArch64 PCS is explicit about return types and argument types being 3618 // handled identically, so we don't need to draw a distinction between 3619 // Argument and Return classification. 3620 ABIArgInfo classifyGenericType(QualType Ty, int &FreeIntRegs, 3621 int &FreeVFPRegs) const; 3622 3623 ABIArgInfo tryUseRegs(QualType Ty, int &FreeRegs, int RegsNeeded, bool IsInt, 3624 llvm::Type *DirectTy = 0) const; 3625 3626 virtual void computeInfo(CGFunctionInfo &FI) const; 3627 3628 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3629 CodeGenFunction &CGF) const; 3630 }; 3631 3632 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo { 3633 public: 3634 AArch64TargetCodeGenInfo(CodeGenTypes &CGT) 3635 :TargetCodeGenInfo(new AArch64ABIInfo(CGT)) {} 3636 3637 const AArch64ABIInfo &getABIInfo() const { 3638 return static_cast<const AArch64ABIInfo&>(TargetCodeGenInfo::getABIInfo()); 3639 } 3640 3641 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 3642 return 31; 3643 } 3644 3645 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 3646 llvm::Value *Address) const { 3647 // 0-31 are x0-x30 and sp: 8 bytes each 3648 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 3649 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 31); 3650 3651 // 64-95 are v0-v31: 16 bytes each 3652 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16); 3653 AssignToArrayRange(CGF.Builder, Address, Sixteen8, 64, 95); 3654 3655 return false; 3656 } 3657 3658 }; 3659 3660 } 3661 3662 void AArch64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 3663 int FreeIntRegs = 8, FreeVFPRegs = 8; 3664 3665 FI.getReturnInfo() = classifyGenericType(FI.getReturnType(), 3666 FreeIntRegs, FreeVFPRegs); 3667 3668 FreeIntRegs = FreeVFPRegs = 8; 3669 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 3670 it != ie; ++it) { 3671 it->info = classifyGenericType(it->type, FreeIntRegs, FreeVFPRegs); 3672 3673 } 3674 } 3675 3676 ABIArgInfo 3677 AArch64ABIInfo::tryUseRegs(QualType Ty, int &FreeRegs, int RegsNeeded, 3678 bool IsInt, llvm::Type *DirectTy) const { 3679 if (FreeRegs >= RegsNeeded) { 3680 FreeRegs -= RegsNeeded; 3681 return ABIArgInfo::getDirect(DirectTy); 3682 } 3683 3684 llvm::Type *Padding = 0; 3685 3686 // We need padding so that later arguments don't get filled in anyway. That 3687 // wouldn't happen if only ByVal arguments followed in the same category, but 3688 // a large structure will simply seem to be a pointer as far as LLVM is 3689 // concerned. 3690 if (FreeRegs > 0) { 3691 if (IsInt) 3692 Padding = llvm::Type::getInt64Ty(getVMContext()); 3693 else 3694 Padding = llvm::Type::getFloatTy(getVMContext()); 3695 3696 // Either [N x i64] or [N x float]. 3697 Padding = llvm::ArrayType::get(Padding, FreeRegs); 3698 FreeRegs = 0; 3699 } 3700 3701 return ABIArgInfo::getIndirect(getContext().getTypeAlign(Ty) / 8, 3702 /*IsByVal=*/ true, /*Realign=*/ false, 3703 Padding); 3704 } 3705 3706 3707 ABIArgInfo AArch64ABIInfo::classifyGenericType(QualType Ty, 3708 int &FreeIntRegs, 3709 int &FreeVFPRegs) const { 3710 // Can only occurs for return, but harmless otherwise. 3711 if (Ty->isVoidType()) 3712 return ABIArgInfo::getIgnore(); 3713 3714 // Large vector types should be returned via memory. There's no such concept 3715 // in the ABI, but they'd be over 16 bytes anyway so no matter how they're 3716 // classified they'd go into memory (see B.3). 3717 if (Ty->isVectorType() && getContext().getTypeSize(Ty) > 128) { 3718 if (FreeIntRegs > 0) 3719 --FreeIntRegs; 3720 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3721 } 3722 3723 // All non-aggregate LLVM types have a concrete ABI representation so they can 3724 // be passed directly. After this block we're guaranteed to be in a 3725 // complicated case. 3726 if (!isAggregateTypeForABI(Ty)) { 3727 // Treat an enum type as its underlying type. 3728 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 3729 Ty = EnumTy->getDecl()->getIntegerType(); 3730 3731 if (Ty->isFloatingType() || Ty->isVectorType()) 3732 return tryUseRegs(Ty, FreeVFPRegs, /*RegsNeeded=*/ 1, /*IsInt=*/ false); 3733 3734 assert(getContext().getTypeSize(Ty) <= 128 && 3735 "unexpectedly large scalar type"); 3736 3737 int RegsNeeded = getContext().getTypeSize(Ty) > 64 ? 2 : 1; 3738 3739 // If the type may need padding registers to ensure "alignment", we must be 3740 // careful when this is accounted for. Increasing the effective size covers 3741 // all cases. 3742 if (getContext().getTypeAlign(Ty) == 128) 3743 RegsNeeded += FreeIntRegs % 2 != 0; 3744 3745 return tryUseRegs(Ty, FreeIntRegs, RegsNeeded, /*IsInt=*/ true); 3746 } 3747 3748 // Structures with either a non-trivial destructor or a non-trivial 3749 // copy constructor are always indirect. 3750 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) { 3751 if (FreeIntRegs > 0) 3752 --FreeIntRegs; 3753 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3754 } 3755 3756 if (isEmptyRecord(getContext(), Ty, true)) { 3757 if (!getContext().getLangOpts().CPlusPlus) { 3758 // Empty structs outside C++ mode are a GNU extension, so no ABI can 3759 // possibly tell us what to do. It turns out (I believe) that GCC ignores 3760 // the object for parameter-passsing purposes. 3761 return ABIArgInfo::getIgnore(); 3762 } 3763 3764 // The combination of C++98 9p5 (sizeof(struct) != 0) and the pseudocode 3765 // description of va_arg in the PCS require that an empty struct does 3766 // actually occupy space for parameter-passing. I'm hoping for a 3767 // clarification giving an explicit paragraph to point to in future. 3768 return tryUseRegs(Ty, FreeIntRegs, /*RegsNeeded=*/ 1, /*IsInt=*/ true, 3769 llvm::Type::getInt8Ty(getVMContext())); 3770 } 3771 3772 // Homogeneous vector aggregates get passed in registers or on the stack. 3773 const Type *Base = 0; 3774 uint64_t NumMembers = 0; 3775 if (isHomogeneousAggregate(Ty, Base, getContext(), &NumMembers)) { 3776 assert(Base && "Base class should be set for homogeneous aggregate"); 3777 // Homogeneous aggregates are passed and returned directly. 3778 return tryUseRegs(Ty, FreeVFPRegs, /*RegsNeeded=*/ NumMembers, 3779 /*IsInt=*/ false); 3780 } 3781 3782 uint64_t Size = getContext().getTypeSize(Ty); 3783 if (Size <= 128) { 3784 // Small structs can use the same direct type whether they're in registers 3785 // or on the stack. 3786 llvm::Type *BaseTy; 3787 unsigned NumBases; 3788 int SizeInRegs = (Size + 63) / 64; 3789 3790 if (getContext().getTypeAlign(Ty) == 128) { 3791 BaseTy = llvm::Type::getIntNTy(getVMContext(), 128); 3792 NumBases = 1; 3793 3794 // If the type may need padding registers to ensure "alignment", we must 3795 // be careful when this is accounted for. Increasing the effective size 3796 // covers all cases. 3797 SizeInRegs += FreeIntRegs % 2 != 0; 3798 } else { 3799 BaseTy = llvm::Type::getInt64Ty(getVMContext()); 3800 NumBases = SizeInRegs; 3801 } 3802 llvm::Type *DirectTy = llvm::ArrayType::get(BaseTy, NumBases); 3803 3804 return tryUseRegs(Ty, FreeIntRegs, /*RegsNeeded=*/ SizeInRegs, 3805 /*IsInt=*/ true, DirectTy); 3806 } 3807 3808 // If the aggregate is > 16 bytes, it's passed and returned indirectly. In 3809 // LLVM terms the return uses an "sret" pointer, but that's handled elsewhere. 3810 --FreeIntRegs; 3811 return ABIArgInfo::getIndirect(0, /* byVal = */ false); 3812 } 3813 3814 llvm::Value *AArch64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3815 CodeGenFunction &CGF) const { 3816 // The AArch64 va_list type and handling is specified in the Procedure Call 3817 // Standard, section B.4: 3818 // 3819 // struct { 3820 // void *__stack; 3821 // void *__gr_top; 3822 // void *__vr_top; 3823 // int __gr_offs; 3824 // int __vr_offs; 3825 // }; 3826 3827 assert(!CGF.CGM.getDataLayout().isBigEndian() 3828 && "va_arg not implemented for big-endian AArch64"); 3829 3830 int FreeIntRegs = 8, FreeVFPRegs = 8; 3831 Ty = CGF.getContext().getCanonicalType(Ty); 3832 ABIArgInfo AI = classifyGenericType(Ty, FreeIntRegs, FreeVFPRegs); 3833 3834 llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg"); 3835 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 3836 llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack"); 3837 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 3838 3839 llvm::Value *reg_offs_p = 0, *reg_offs = 0; 3840 int reg_top_index; 3841 int RegSize; 3842 if (FreeIntRegs < 8) { 3843 assert(FreeVFPRegs == 8 && "Arguments never split between int & VFP regs"); 3844 // 3 is the field number of __gr_offs 3845 reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 3, "gr_offs_p"); 3846 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs"); 3847 reg_top_index = 1; // field number for __gr_top 3848 RegSize = 8 * (8 - FreeIntRegs); 3849 } else { 3850 assert(FreeVFPRegs < 8 && "Argument must go in VFP or int regs"); 3851 // 4 is the field number of __vr_offs. 3852 reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 4, "vr_offs_p"); 3853 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs"); 3854 reg_top_index = 2; // field number for __vr_top 3855 RegSize = 16 * (8 - FreeVFPRegs); 3856 } 3857 3858 //======================================= 3859 // Find out where argument was passed 3860 //======================================= 3861 3862 // If reg_offs >= 0 we're already using the stack for this type of 3863 // argument. We don't want to keep updating reg_offs (in case it overflows, 3864 // though anyone passing 2GB of arguments, each at most 16 bytes, deserves 3865 // whatever they get). 3866 llvm::Value *UsingStack = 0; 3867 UsingStack = CGF.Builder.CreateICmpSGE(reg_offs, 3868 llvm::ConstantInt::get(CGF.Int32Ty, 0)); 3869 3870 CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock); 3871 3872 // Otherwise, at least some kind of argument could go in these registers, the 3873 // quesiton is whether this particular type is too big. 3874 CGF.EmitBlock(MaybeRegBlock); 3875 3876 // Integer arguments may need to correct register alignment (for example a 3877 // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we 3878 // align __gr_offs to calculate the potential address. 3879 if (FreeIntRegs < 8 && AI.isDirect() && getContext().getTypeAlign(Ty) > 64) { 3880 int Align = getContext().getTypeAlign(Ty) / 8; 3881 3882 reg_offs = CGF.Builder.CreateAdd(reg_offs, 3883 llvm::ConstantInt::get(CGF.Int32Ty, Align - 1), 3884 "align_regoffs"); 3885 reg_offs = CGF.Builder.CreateAnd(reg_offs, 3886 llvm::ConstantInt::get(CGF.Int32Ty, -Align), 3887 "aligned_regoffs"); 3888 } 3889 3890 // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list. 3891 llvm::Value *NewOffset = 0; 3892 NewOffset = CGF.Builder.CreateAdd(reg_offs, 3893 llvm::ConstantInt::get(CGF.Int32Ty, RegSize), 3894 "new_reg_offs"); 3895 CGF.Builder.CreateStore(NewOffset, reg_offs_p); 3896 3897 // Now we're in a position to decide whether this argument really was in 3898 // registers or not. 3899 llvm::Value *InRegs = 0; 3900 InRegs = CGF.Builder.CreateICmpSLE(NewOffset, 3901 llvm::ConstantInt::get(CGF.Int32Ty, 0), 3902 "inreg"); 3903 3904 CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock); 3905 3906 //======================================= 3907 // Argument was in registers 3908 //======================================= 3909 3910 // Now we emit the code for if the argument was originally passed in 3911 // registers. First start the appropriate block: 3912 CGF.EmitBlock(InRegBlock); 3913 3914 llvm::Value *reg_top_p = 0, *reg_top = 0; 3915 reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index, "reg_top_p"); 3916 reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top"); 3917 llvm::Value *BaseAddr = CGF.Builder.CreateGEP(reg_top, reg_offs); 3918 llvm::Value *RegAddr = 0; 3919 llvm::Type *MemTy = llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty)); 3920 3921 if (!AI.isDirect()) { 3922 // If it's been passed indirectly (actually a struct), whatever we find from 3923 // stored registers or on the stack will actually be a struct **. 3924 MemTy = llvm::PointerType::getUnqual(MemTy); 3925 } 3926 3927 const Type *Base = 0; 3928 uint64_t NumMembers; 3929 if (isHomogeneousAggregate(Ty, Base, getContext(), &NumMembers) 3930 && NumMembers > 1) { 3931 // Homogeneous aggregates passed in registers will have their elements split 3932 // and stored 16-bytes apart regardless of size (they're notionally in qN, 3933 // qN+1, ...). We reload and store into a temporary local variable 3934 // contiguously. 3935 assert(AI.isDirect() && "Homogeneous aggregates should be passed directly"); 3936 llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0)); 3937 llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers); 3938 llvm::Value *Tmp = CGF.CreateTempAlloca(HFATy); 3939 3940 for (unsigned i = 0; i < NumMembers; ++i) { 3941 llvm::Value *BaseOffset = llvm::ConstantInt::get(CGF.Int32Ty, 16 * i); 3942 llvm::Value *LoadAddr = CGF.Builder.CreateGEP(BaseAddr, BaseOffset); 3943 LoadAddr = CGF.Builder.CreateBitCast(LoadAddr, 3944 llvm::PointerType::getUnqual(BaseTy)); 3945 llvm::Value *StoreAddr = CGF.Builder.CreateStructGEP(Tmp, i); 3946 3947 llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr); 3948 CGF.Builder.CreateStore(Elem, StoreAddr); 3949 } 3950 3951 RegAddr = CGF.Builder.CreateBitCast(Tmp, MemTy); 3952 } else { 3953 // Otherwise the object is contiguous in memory 3954 RegAddr = CGF.Builder.CreateBitCast(BaseAddr, MemTy); 3955 } 3956 3957 CGF.EmitBranch(ContBlock); 3958 3959 //======================================= 3960 // Argument was on the stack 3961 //======================================= 3962 CGF.EmitBlock(OnStackBlock); 3963 3964 llvm::Value *stack_p = 0, *OnStackAddr = 0; 3965 stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "stack_p"); 3966 OnStackAddr = CGF.Builder.CreateLoad(stack_p, "stack"); 3967 3968 // Again, stack arguments may need realigmnent. In this case both integer and 3969 // floating-point ones might be affected. 3970 if (AI.isDirect() && getContext().getTypeAlign(Ty) > 64) { 3971 int Align = getContext().getTypeAlign(Ty) / 8; 3972 3973 OnStackAddr = CGF.Builder.CreatePtrToInt(OnStackAddr, CGF.Int64Ty); 3974 3975 OnStackAddr = CGF.Builder.CreateAdd(OnStackAddr, 3976 llvm::ConstantInt::get(CGF.Int64Ty, Align - 1), 3977 "align_stack"); 3978 OnStackAddr = CGF.Builder.CreateAnd(OnStackAddr, 3979 llvm::ConstantInt::get(CGF.Int64Ty, -Align), 3980 "align_stack"); 3981 3982 OnStackAddr = CGF.Builder.CreateIntToPtr(OnStackAddr, CGF.Int8PtrTy); 3983 } 3984 3985 uint64_t StackSize; 3986 if (AI.isDirect()) 3987 StackSize = getContext().getTypeSize(Ty) / 8; 3988 else 3989 StackSize = 8; 3990 3991 // All stack slots are 8 bytes 3992 StackSize = llvm::RoundUpToAlignment(StackSize, 8); 3993 3994 llvm::Value *StackSizeC = llvm::ConstantInt::get(CGF.Int32Ty, StackSize); 3995 llvm::Value *NewStack = CGF.Builder.CreateGEP(OnStackAddr, StackSizeC, 3996 "new_stack"); 3997 3998 // Write the new value of __stack for the next call to va_arg 3999 CGF.Builder.CreateStore(NewStack, stack_p); 4000 4001 OnStackAddr = CGF.Builder.CreateBitCast(OnStackAddr, MemTy); 4002 4003 CGF.EmitBranch(ContBlock); 4004 4005 //======================================= 4006 // Tidy up 4007 //======================================= 4008 CGF.EmitBlock(ContBlock); 4009 4010 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(MemTy, 2, "vaarg.addr"); 4011 ResAddr->addIncoming(RegAddr, InRegBlock); 4012 ResAddr->addIncoming(OnStackAddr, OnStackBlock); 4013 4014 if (AI.isDirect()) 4015 return ResAddr; 4016 4017 return CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"); 4018 } 4019 4020 //===----------------------------------------------------------------------===// 4021 // NVPTX ABI Implementation 4022 //===----------------------------------------------------------------------===// 4023 4024 namespace { 4025 4026 class NVPTXABIInfo : public ABIInfo { 4027 public: 4028 NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) { setRuntimeCC(); } 4029 4030 ABIArgInfo classifyReturnType(QualType RetTy) const; 4031 ABIArgInfo classifyArgumentType(QualType Ty) const; 4032 4033 virtual void computeInfo(CGFunctionInfo &FI) const; 4034 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4035 CodeGenFunction &CFG) const; 4036 private: 4037 void setRuntimeCC(); 4038 }; 4039 4040 class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo { 4041 public: 4042 NVPTXTargetCodeGenInfo(CodeGenTypes &CGT) 4043 : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {} 4044 4045 virtual void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4046 CodeGen::CodeGenModule &M) const; 4047 }; 4048 4049 ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const { 4050 if (RetTy->isVoidType()) 4051 return ABIArgInfo::getIgnore(); 4052 if (isAggregateTypeForABI(RetTy)) 4053 return ABIArgInfo::getIndirect(0); 4054 return ABIArgInfo::getDirect(); 4055 } 4056 4057 ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const { 4058 if (isAggregateTypeForABI(Ty)) 4059 return ABIArgInfo::getIndirect(0); 4060 4061 return ABIArgInfo::getDirect(); 4062 } 4063 4064 void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const { 4065 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4066 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4067 it != ie; ++it) 4068 it->info = classifyArgumentType(it->type); 4069 4070 // Always honor user-specified calling convention. 4071 if (FI.getCallingConvention() != llvm::CallingConv::C) 4072 return; 4073 4074 FI.setEffectiveCallingConvention(getRuntimeCC()); 4075 } 4076 4077 void NVPTXABIInfo::setRuntimeCC() { 4078 // Calling convention as default by an ABI. 4079 // We're still using the PTX_Kernel/PTX_Device calling conventions here, 4080 // but we should switch to NVVM metadata later on. 4081 const LangOptions &LangOpts = getContext().getLangOpts(); 4082 if (LangOpts.OpenCL || LangOpts.CUDA) { 4083 // If we are in OpenCL or CUDA mode, then default to device functions 4084 RuntimeCC = llvm::CallingConv::PTX_Device; 4085 } else { 4086 // If we are in standard C/C++ mode, use the triple to decide on the default 4087 StringRef Env = 4088 getContext().getTargetInfo().getTriple().getEnvironmentName(); 4089 if (Env == "device") 4090 RuntimeCC = llvm::CallingConv::PTX_Device; 4091 else 4092 RuntimeCC = llvm::CallingConv::PTX_Kernel; 4093 } 4094 } 4095 4096 llvm::Value *NVPTXABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4097 CodeGenFunction &CFG) const { 4098 llvm_unreachable("NVPTX does not support varargs"); 4099 } 4100 4101 void NVPTXTargetCodeGenInfo:: 4102 SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4103 CodeGen::CodeGenModule &M) const{ 4104 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4105 if (!FD) return; 4106 4107 llvm::Function *F = cast<llvm::Function>(GV); 4108 4109 // Perform special handling in OpenCL mode 4110 if (M.getLangOpts().OpenCL) { 4111 // Use OpenCL function attributes to set proper calling conventions 4112 // By default, all functions are device functions 4113 if (FD->hasAttr<OpenCLKernelAttr>()) { 4114 // OpenCL __kernel functions get a kernel calling convention 4115 F->setCallingConv(llvm::CallingConv::PTX_Kernel); 4116 // And kernel functions are not subject to inlining 4117 F->addFnAttr(llvm::Attribute::NoInline); 4118 } 4119 } 4120 4121 // Perform special handling in CUDA mode. 4122 if (M.getLangOpts().CUDA) { 4123 // CUDA __global__ functions get a kernel calling convention. Since 4124 // __global__ functions cannot be called from the device, we do not 4125 // need to set the noinline attribute. 4126 if (FD->getAttr<CUDAGlobalAttr>()) 4127 F->setCallingConv(llvm::CallingConv::PTX_Kernel); 4128 } 4129 } 4130 4131 } 4132 4133 //===----------------------------------------------------------------------===// 4134 // MBlaze ABI Implementation 4135 //===----------------------------------------------------------------------===// 4136 4137 namespace { 4138 4139 class MBlazeABIInfo : public ABIInfo { 4140 public: 4141 MBlazeABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 4142 4143 bool isPromotableIntegerType(QualType Ty) const; 4144 4145 ABIArgInfo classifyReturnType(QualType RetTy) const; 4146 ABIArgInfo classifyArgumentType(QualType RetTy) const; 4147 4148 virtual void computeInfo(CGFunctionInfo &FI) const { 4149 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4150 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4151 it != ie; ++it) 4152 it->info = classifyArgumentType(it->type); 4153 } 4154 4155 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4156 CodeGenFunction &CGF) const; 4157 }; 4158 4159 class MBlazeTargetCodeGenInfo : public TargetCodeGenInfo { 4160 public: 4161 MBlazeTargetCodeGenInfo(CodeGenTypes &CGT) 4162 : TargetCodeGenInfo(new MBlazeABIInfo(CGT)) {} 4163 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4164 CodeGen::CodeGenModule &M) const; 4165 }; 4166 4167 } 4168 4169 bool MBlazeABIInfo::isPromotableIntegerType(QualType Ty) const { 4170 // MBlaze ABI requires all 8 and 16 bit quantities to be extended. 4171 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 4172 switch (BT->getKind()) { 4173 case BuiltinType::Bool: 4174 case BuiltinType::Char_S: 4175 case BuiltinType::Char_U: 4176 case BuiltinType::SChar: 4177 case BuiltinType::UChar: 4178 case BuiltinType::Short: 4179 case BuiltinType::UShort: 4180 return true; 4181 default: 4182 return false; 4183 } 4184 return false; 4185 } 4186 4187 llvm::Value *MBlazeABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4188 CodeGenFunction &CGF) const { 4189 // FIXME: Implement 4190 return 0; 4191 } 4192 4193 4194 ABIArgInfo MBlazeABIInfo::classifyReturnType(QualType RetTy) const { 4195 if (RetTy->isVoidType()) 4196 return ABIArgInfo::getIgnore(); 4197 if (isAggregateTypeForABI(RetTy)) 4198 return ABIArgInfo::getIndirect(0); 4199 4200 return (isPromotableIntegerType(RetTy) ? 4201 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4202 } 4203 4204 ABIArgInfo MBlazeABIInfo::classifyArgumentType(QualType Ty) const { 4205 if (isAggregateTypeForABI(Ty)) 4206 return ABIArgInfo::getIndirect(0); 4207 4208 return (isPromotableIntegerType(Ty) ? 4209 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4210 } 4211 4212 void MBlazeTargetCodeGenInfo::SetTargetAttributes(const Decl *D, 4213 llvm::GlobalValue *GV, 4214 CodeGen::CodeGenModule &M) 4215 const { 4216 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4217 if (!FD) return; 4218 4219 llvm::CallingConv::ID CC = llvm::CallingConv::C; 4220 if (FD->hasAttr<MBlazeInterruptHandlerAttr>()) 4221 CC = llvm::CallingConv::MBLAZE_INTR; 4222 else if (FD->hasAttr<MBlazeSaveVolatilesAttr>()) 4223 CC = llvm::CallingConv::MBLAZE_SVOL; 4224 4225 if (CC != llvm::CallingConv::C) { 4226 // Handle 'interrupt_handler' attribute: 4227 llvm::Function *F = cast<llvm::Function>(GV); 4228 4229 // Step 1: Set ISR calling convention. 4230 F->setCallingConv(CC); 4231 4232 // Step 2: Add attributes goodness. 4233 F->addFnAttr(llvm::Attribute::NoInline); 4234 } 4235 4236 // Step 3: Emit _interrupt_handler alias. 4237 if (CC == llvm::CallingConv::MBLAZE_INTR) 4238 new llvm::GlobalAlias(GV->getType(), llvm::Function::ExternalLinkage, 4239 "_interrupt_handler", GV, &M.getModule()); 4240 } 4241 4242 4243 //===----------------------------------------------------------------------===// 4244 // MSP430 ABI Implementation 4245 //===----------------------------------------------------------------------===// 4246 4247 namespace { 4248 4249 class MSP430TargetCodeGenInfo : public TargetCodeGenInfo { 4250 public: 4251 MSP430TargetCodeGenInfo(CodeGenTypes &CGT) 4252 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 4253 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4254 CodeGen::CodeGenModule &M) const; 4255 }; 4256 4257 } 4258 4259 void MSP430TargetCodeGenInfo::SetTargetAttributes(const Decl *D, 4260 llvm::GlobalValue *GV, 4261 CodeGen::CodeGenModule &M) const { 4262 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) { 4263 if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) { 4264 // Handle 'interrupt' attribute: 4265 llvm::Function *F = cast<llvm::Function>(GV); 4266 4267 // Step 1: Set ISR calling convention. 4268 F->setCallingConv(llvm::CallingConv::MSP430_INTR); 4269 4270 // Step 2: Add attributes goodness. 4271 F->addFnAttr(llvm::Attribute::NoInline); 4272 4273 // Step 3: Emit ISR vector alias. 4274 unsigned Num = attr->getNumber() / 2; 4275 new llvm::GlobalAlias(GV->getType(), llvm::Function::ExternalLinkage, 4276 "__isr_" + Twine(Num), 4277 GV, &M.getModule()); 4278 } 4279 } 4280 } 4281 4282 //===----------------------------------------------------------------------===// 4283 // MIPS ABI Implementation. This works for both little-endian and 4284 // big-endian variants. 4285 //===----------------------------------------------------------------------===// 4286 4287 namespace { 4288 class MipsABIInfo : public ABIInfo { 4289 bool IsO32; 4290 unsigned MinABIStackAlignInBytes, StackAlignInBytes; 4291 void CoerceToIntArgs(uint64_t TySize, 4292 SmallVector<llvm::Type*, 8> &ArgList) const; 4293 llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const; 4294 llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const; 4295 llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const; 4296 public: 4297 MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) : 4298 ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8), 4299 StackAlignInBytes(IsO32 ? 8 : 16) {} 4300 4301 ABIArgInfo classifyReturnType(QualType RetTy) const; 4302 ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const; 4303 virtual void computeInfo(CGFunctionInfo &FI) const; 4304 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4305 CodeGenFunction &CGF) const; 4306 }; 4307 4308 class MIPSTargetCodeGenInfo : public TargetCodeGenInfo { 4309 unsigned SizeOfUnwindException; 4310 public: 4311 MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32) 4312 : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)), 4313 SizeOfUnwindException(IsO32 ? 24 : 32) {} 4314 4315 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 4316 return 29; 4317 } 4318 4319 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4320 CodeGen::CodeGenModule &CGM) const { 4321 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4322 if (!FD) return; 4323 llvm::Function *Fn = dyn_cast<llvm::Function>(GV); 4324 if (!Fn) return; // should not happen 4325 if (FD->hasAttr<Mips16Attr>()) { 4326 Fn->addFnAttr("mips16"); 4327 } 4328 else if (FD->hasAttr<NoMips16Attr>()) { 4329 Fn->addFnAttr("nomips16"); 4330 } 4331 } 4332 4333 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4334 llvm::Value *Address) const; 4335 4336 unsigned getSizeOfUnwindException() const { 4337 return SizeOfUnwindException; 4338 } 4339 }; 4340 } 4341 4342 void MipsABIInfo::CoerceToIntArgs(uint64_t TySize, 4343 SmallVector<llvm::Type*, 8> &ArgList) const { 4344 llvm::IntegerType *IntTy = 4345 llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8); 4346 4347 // Add (TySize / MinABIStackAlignInBytes) args of IntTy. 4348 for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N) 4349 ArgList.push_back(IntTy); 4350 4351 // If necessary, add one more integer type to ArgList. 4352 unsigned R = TySize % (MinABIStackAlignInBytes * 8); 4353 4354 if (R) 4355 ArgList.push_back(llvm::IntegerType::get(getVMContext(), R)); 4356 } 4357 4358 // In N32/64, an aligned double precision floating point field is passed in 4359 // a register. 4360 llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const { 4361 SmallVector<llvm::Type*, 8> ArgList, IntArgList; 4362 4363 if (IsO32) { 4364 CoerceToIntArgs(TySize, ArgList); 4365 return llvm::StructType::get(getVMContext(), ArgList); 4366 } 4367 4368 if (Ty->isComplexType()) 4369 return CGT.ConvertType(Ty); 4370 4371 const RecordType *RT = Ty->getAs<RecordType>(); 4372 4373 // Unions/vectors are passed in integer registers. 4374 if (!RT || !RT->isStructureOrClassType()) { 4375 CoerceToIntArgs(TySize, ArgList); 4376 return llvm::StructType::get(getVMContext(), ArgList); 4377 } 4378 4379 const RecordDecl *RD = RT->getDecl(); 4380 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 4381 assert(!(TySize % 8) && "Size of structure must be multiple of 8."); 4382 4383 uint64_t LastOffset = 0; 4384 unsigned idx = 0; 4385 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64); 4386 4387 // Iterate over fields in the struct/class and check if there are any aligned 4388 // double fields. 4389 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 4390 i != e; ++i, ++idx) { 4391 const QualType Ty = i->getType(); 4392 const BuiltinType *BT = Ty->getAs<BuiltinType>(); 4393 4394 if (!BT || BT->getKind() != BuiltinType::Double) 4395 continue; 4396 4397 uint64_t Offset = Layout.getFieldOffset(idx); 4398 if (Offset % 64) // Ignore doubles that are not aligned. 4399 continue; 4400 4401 // Add ((Offset - LastOffset) / 64) args of type i64. 4402 for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j) 4403 ArgList.push_back(I64); 4404 4405 // Add double type. 4406 ArgList.push_back(llvm::Type::getDoubleTy(getVMContext())); 4407 LastOffset = Offset + 64; 4408 } 4409 4410 CoerceToIntArgs(TySize - LastOffset, IntArgList); 4411 ArgList.append(IntArgList.begin(), IntArgList.end()); 4412 4413 return llvm::StructType::get(getVMContext(), ArgList); 4414 } 4415 4416 llvm::Type *MipsABIInfo::getPaddingType(uint64_t Align, uint64_t Offset) const { 4417 assert((Offset % MinABIStackAlignInBytes) == 0); 4418 4419 if ((Align - 1) & Offset) 4420 return llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8); 4421 4422 return 0; 4423 } 4424 4425 ABIArgInfo 4426 MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const { 4427 uint64_t OrigOffset = Offset; 4428 uint64_t TySize = getContext().getTypeSize(Ty); 4429 uint64_t Align = getContext().getTypeAlign(Ty) / 8; 4430 4431 Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes), 4432 (uint64_t)StackAlignInBytes); 4433 Offset = llvm::RoundUpToAlignment(Offset, Align); 4434 Offset += llvm::RoundUpToAlignment(TySize, Align * 8) / 8; 4435 4436 if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) { 4437 // Ignore empty aggregates. 4438 if (TySize == 0) 4439 return ABIArgInfo::getIgnore(); 4440 4441 // Records with non trivial destructors/constructors should not be passed 4442 // by value. 4443 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) { 4444 Offset = OrigOffset + MinABIStackAlignInBytes; 4445 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 4446 } 4447 4448 // If we have reached here, aggregates are passed directly by coercing to 4449 // another structure type. Padding is inserted if the offset of the 4450 // aggregate is unaligned. 4451 return ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0, 4452 getPaddingType(Align, OrigOffset)); 4453 } 4454 4455 // Treat an enum type as its underlying type. 4456 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 4457 Ty = EnumTy->getDecl()->getIntegerType(); 4458 4459 if (Ty->isPromotableIntegerType()) 4460 return ABIArgInfo::getExtend(); 4461 4462 return ABIArgInfo::getDirect(0, 0, 4463 IsO32 ? 0 : getPaddingType(Align, OrigOffset)); 4464 } 4465 4466 llvm::Type* 4467 MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const { 4468 const RecordType *RT = RetTy->getAs<RecordType>(); 4469 SmallVector<llvm::Type*, 8> RTList; 4470 4471 if (RT && RT->isStructureOrClassType()) { 4472 const RecordDecl *RD = RT->getDecl(); 4473 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 4474 unsigned FieldCnt = Layout.getFieldCount(); 4475 4476 // N32/64 returns struct/classes in floating point registers if the 4477 // following conditions are met: 4478 // 1. The size of the struct/class is no larger than 128-bit. 4479 // 2. The struct/class has one or two fields all of which are floating 4480 // point types. 4481 // 3. The offset of the first field is zero (this follows what gcc does). 4482 // 4483 // Any other composite results are returned in integer registers. 4484 // 4485 if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) { 4486 RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end(); 4487 for (; b != e; ++b) { 4488 const BuiltinType *BT = b->getType()->getAs<BuiltinType>(); 4489 4490 if (!BT || !BT->isFloatingPoint()) 4491 break; 4492 4493 RTList.push_back(CGT.ConvertType(b->getType())); 4494 } 4495 4496 if (b == e) 4497 return llvm::StructType::get(getVMContext(), RTList, 4498 RD->hasAttr<PackedAttr>()); 4499 4500 RTList.clear(); 4501 } 4502 } 4503 4504 CoerceToIntArgs(Size, RTList); 4505 return llvm::StructType::get(getVMContext(), RTList); 4506 } 4507 4508 ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const { 4509 uint64_t Size = getContext().getTypeSize(RetTy); 4510 4511 if (RetTy->isVoidType() || Size == 0) 4512 return ABIArgInfo::getIgnore(); 4513 4514 if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) { 4515 if (Size <= 128) { 4516 if (RetTy->isAnyComplexType()) 4517 return ABIArgInfo::getDirect(); 4518 4519 // O32 returns integer vectors in registers. 4520 if (IsO32 && RetTy->isVectorType() && !RetTy->hasFloatingRepresentation()) 4521 return ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); 4522 4523 if (!IsO32 && !isRecordWithNonTrivialDestructorOrCopyConstructor(RetTy)) 4524 return ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); 4525 } 4526 4527 return ABIArgInfo::getIndirect(0); 4528 } 4529 4530 // Treat an enum type as its underlying type. 4531 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 4532 RetTy = EnumTy->getDecl()->getIntegerType(); 4533 4534 return (RetTy->isPromotableIntegerType() ? 4535 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4536 } 4537 4538 void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const { 4539 ABIArgInfo &RetInfo = FI.getReturnInfo(); 4540 RetInfo = classifyReturnType(FI.getReturnType()); 4541 4542 // Check if a pointer to an aggregate is passed as a hidden argument. 4543 uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0; 4544 4545 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4546 it != ie; ++it) 4547 it->info = classifyArgumentType(it->type, Offset); 4548 } 4549 4550 llvm::Value* MipsABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4551 CodeGenFunction &CGF) const { 4552 llvm::Type *BP = CGF.Int8PtrTy; 4553 llvm::Type *BPP = CGF.Int8PtrPtrTy; 4554 4555 CGBuilderTy &Builder = CGF.Builder; 4556 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 4557 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 4558 int64_t TypeAlign = getContext().getTypeAlign(Ty) / 8; 4559 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 4560 llvm::Value *AddrTyped; 4561 unsigned PtrWidth = getContext().getTargetInfo().getPointerWidth(0); 4562 llvm::IntegerType *IntTy = (PtrWidth == 32) ? CGF.Int32Ty : CGF.Int64Ty; 4563 4564 if (TypeAlign > MinABIStackAlignInBytes) { 4565 llvm::Value *AddrAsInt = CGF.Builder.CreatePtrToInt(Addr, IntTy); 4566 llvm::Value *Inc = llvm::ConstantInt::get(IntTy, TypeAlign - 1); 4567 llvm::Value *Mask = llvm::ConstantInt::get(IntTy, -TypeAlign); 4568 llvm::Value *Add = CGF.Builder.CreateAdd(AddrAsInt, Inc); 4569 llvm::Value *And = CGF.Builder.CreateAnd(Add, Mask); 4570 AddrTyped = CGF.Builder.CreateIntToPtr(And, PTy); 4571 } 4572 else 4573 AddrTyped = Builder.CreateBitCast(Addr, PTy); 4574 4575 llvm::Value *AlignedAddr = Builder.CreateBitCast(AddrTyped, BP); 4576 TypeAlign = std::max((unsigned)TypeAlign, MinABIStackAlignInBytes); 4577 uint64_t Offset = 4578 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, TypeAlign); 4579 llvm::Value *NextAddr = 4580 Builder.CreateGEP(AlignedAddr, llvm::ConstantInt::get(IntTy, Offset), 4581 "ap.next"); 4582 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 4583 4584 return AddrTyped; 4585 } 4586 4587 bool 4588 MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4589 llvm::Value *Address) const { 4590 // This information comes from gcc's implementation, which seems to 4591 // as canonical as it gets. 4592 4593 // Everything on MIPS is 4 bytes. Double-precision FP registers 4594 // are aliased to pairs of single-precision FP registers. 4595 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 4596 4597 // 0-31 are the general purpose registers, $0 - $31. 4598 // 32-63 are the floating-point registers, $f0 - $f31. 4599 // 64 and 65 are the multiply/divide registers, $hi and $lo. 4600 // 66 is the (notional, I think) register for signal-handler return. 4601 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65); 4602 4603 // 67-74 are the floating-point status registers, $fcc0 - $fcc7. 4604 // They are one bit wide and ignored here. 4605 4606 // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31. 4607 // (coprocessor 1 is the FP unit) 4608 // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31. 4609 // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31. 4610 // 176-181 are the DSP accumulator registers. 4611 AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181); 4612 return false; 4613 } 4614 4615 //===----------------------------------------------------------------------===// 4616 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults. 4617 // Currently subclassed only to implement custom OpenCL C function attribute 4618 // handling. 4619 //===----------------------------------------------------------------------===// 4620 4621 namespace { 4622 4623 class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo { 4624 public: 4625 TCETargetCodeGenInfo(CodeGenTypes &CGT) 4626 : DefaultTargetCodeGenInfo(CGT) {} 4627 4628 virtual void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4629 CodeGen::CodeGenModule &M) const; 4630 }; 4631 4632 void TCETargetCodeGenInfo::SetTargetAttributes(const Decl *D, 4633 llvm::GlobalValue *GV, 4634 CodeGen::CodeGenModule &M) const { 4635 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4636 if (!FD) return; 4637 4638 llvm::Function *F = cast<llvm::Function>(GV); 4639 4640 if (M.getLangOpts().OpenCL) { 4641 if (FD->hasAttr<OpenCLKernelAttr>()) { 4642 // OpenCL C Kernel functions are not subject to inlining 4643 F->addFnAttr(llvm::Attribute::NoInline); 4644 4645 if (FD->hasAttr<ReqdWorkGroupSizeAttr>()) { 4646 4647 // Convert the reqd_work_group_size() attributes to metadata. 4648 llvm::LLVMContext &Context = F->getContext(); 4649 llvm::NamedMDNode *OpenCLMetadata = 4650 M.getModule().getOrInsertNamedMetadata("opencl.kernel_wg_size_info"); 4651 4652 SmallVector<llvm::Value*, 5> Operands; 4653 Operands.push_back(F); 4654 4655 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 4656 llvm::APInt(32, 4657 FD->getAttr<ReqdWorkGroupSizeAttr>()->getXDim()))); 4658 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 4659 llvm::APInt(32, 4660 FD->getAttr<ReqdWorkGroupSizeAttr>()->getYDim()))); 4661 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 4662 llvm::APInt(32, 4663 FD->getAttr<ReqdWorkGroupSizeAttr>()->getZDim()))); 4664 4665 // Add a boolean constant operand for "required" (true) or "hint" (false) 4666 // for implementing the work_group_size_hint attr later. Currently 4667 // always true as the hint is not yet implemented. 4668 Operands.push_back(llvm::ConstantInt::getTrue(Context)); 4669 OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands)); 4670 } 4671 } 4672 } 4673 } 4674 4675 } 4676 4677 //===----------------------------------------------------------------------===// 4678 // Hexagon ABI Implementation 4679 //===----------------------------------------------------------------------===// 4680 4681 namespace { 4682 4683 class HexagonABIInfo : public ABIInfo { 4684 4685 4686 public: 4687 HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 4688 4689 private: 4690 4691 ABIArgInfo classifyReturnType(QualType RetTy) const; 4692 ABIArgInfo classifyArgumentType(QualType RetTy) const; 4693 4694 virtual void computeInfo(CGFunctionInfo &FI) const; 4695 4696 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4697 CodeGenFunction &CGF) const; 4698 }; 4699 4700 class HexagonTargetCodeGenInfo : public TargetCodeGenInfo { 4701 public: 4702 HexagonTargetCodeGenInfo(CodeGenTypes &CGT) 4703 :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {} 4704 4705 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 4706 return 29; 4707 } 4708 }; 4709 4710 } 4711 4712 void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const { 4713 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4714 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4715 it != ie; ++it) 4716 it->info = classifyArgumentType(it->type); 4717 } 4718 4719 ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const { 4720 if (!isAggregateTypeForABI(Ty)) { 4721 // Treat an enum type as its underlying type. 4722 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 4723 Ty = EnumTy->getDecl()->getIntegerType(); 4724 4725 return (Ty->isPromotableIntegerType() ? 4726 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4727 } 4728 4729 // Ignore empty records. 4730 if (isEmptyRecord(getContext(), Ty, true)) 4731 return ABIArgInfo::getIgnore(); 4732 4733 // Structures with either a non-trivial destructor or a non-trivial 4734 // copy constructor are always indirect. 4735 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 4736 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 4737 4738 uint64_t Size = getContext().getTypeSize(Ty); 4739 if (Size > 64) 4740 return ABIArgInfo::getIndirect(0, /*ByVal=*/true); 4741 // Pass in the smallest viable integer type. 4742 else if (Size > 32) 4743 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); 4744 else if (Size > 16) 4745 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 4746 else if (Size > 8) 4747 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 4748 else 4749 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 4750 } 4751 4752 ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const { 4753 if (RetTy->isVoidType()) 4754 return ABIArgInfo::getIgnore(); 4755 4756 // Large vector types should be returned via memory. 4757 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64) 4758 return ABIArgInfo::getIndirect(0); 4759 4760 if (!isAggregateTypeForABI(RetTy)) { 4761 // Treat an enum type as its underlying type. 4762 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 4763 RetTy = EnumTy->getDecl()->getIntegerType(); 4764 4765 return (RetTy->isPromotableIntegerType() ? 4766 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4767 } 4768 4769 // Structures with either a non-trivial destructor or a non-trivial 4770 // copy constructor are always indirect. 4771 if (isRecordWithNonTrivialDestructorOrCopyConstructor(RetTy)) 4772 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 4773 4774 if (isEmptyRecord(getContext(), RetTy, true)) 4775 return ABIArgInfo::getIgnore(); 4776 4777 // Aggregates <= 8 bytes are returned in r0; other aggregates 4778 // are returned indirectly. 4779 uint64_t Size = getContext().getTypeSize(RetTy); 4780 if (Size <= 64) { 4781 // Return in the smallest viable integer type. 4782 if (Size <= 8) 4783 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 4784 if (Size <= 16) 4785 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 4786 if (Size <= 32) 4787 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 4788 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); 4789 } 4790 4791 return ABIArgInfo::getIndirect(0, /*ByVal=*/true); 4792 } 4793 4794 llvm::Value *HexagonABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4795 CodeGenFunction &CGF) const { 4796 // FIXME: Need to handle alignment 4797 llvm::Type *BPP = CGF.Int8PtrPtrTy; 4798 4799 CGBuilderTy &Builder = CGF.Builder; 4800 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 4801 "ap"); 4802 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 4803 llvm::Type *PTy = 4804 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 4805 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 4806 4807 uint64_t Offset = 4808 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 4); 4809 llvm::Value *NextAddr = 4810 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 4811 "ap.next"); 4812 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 4813 4814 return AddrTyped; 4815 } 4816 4817 4818 const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() { 4819 if (TheTargetCodeGenInfo) 4820 return *TheTargetCodeGenInfo; 4821 4822 const llvm::Triple &Triple = getContext().getTargetInfo().getTriple(); 4823 switch (Triple.getArch()) { 4824 default: 4825 return *(TheTargetCodeGenInfo = new DefaultTargetCodeGenInfo(Types)); 4826 4827 case llvm::Triple::le32: 4828 return *(TheTargetCodeGenInfo = new PNaClTargetCodeGenInfo(Types)); 4829 case llvm::Triple::mips: 4830 case llvm::Triple::mipsel: 4831 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, true)); 4832 4833 case llvm::Triple::mips64: 4834 case llvm::Triple::mips64el: 4835 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, false)); 4836 4837 case llvm::Triple::aarch64: 4838 return *(TheTargetCodeGenInfo = new AArch64TargetCodeGenInfo(Types)); 4839 4840 case llvm::Triple::arm: 4841 case llvm::Triple::thumb: 4842 { 4843 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS; 4844 if (strcmp(getContext().getTargetInfo().getABI(), "apcs-gnu") == 0) 4845 Kind = ARMABIInfo::APCS; 4846 else if (CodeGenOpts.FloatABI == "hard" || 4847 (CodeGenOpts.FloatABI != "soft" && Triple.getEnvironment()==llvm::Triple::GNUEABIHF)) 4848 Kind = ARMABIInfo::AAPCS_VFP; 4849 4850 switch (Triple.getOS()) { 4851 case llvm::Triple::NaCl: 4852 return *(TheTargetCodeGenInfo = 4853 new NaClARMTargetCodeGenInfo(Types, Kind)); 4854 default: 4855 return *(TheTargetCodeGenInfo = 4856 new ARMTargetCodeGenInfo(Types, Kind)); 4857 } 4858 } 4859 4860 case llvm::Triple::ppc: 4861 return *(TheTargetCodeGenInfo = new PPC32TargetCodeGenInfo(Types)); 4862 case llvm::Triple::ppc64: 4863 if (Triple.isOSBinFormatELF()) 4864 return *(TheTargetCodeGenInfo = new PPC64_SVR4_TargetCodeGenInfo(Types)); 4865 else 4866 return *(TheTargetCodeGenInfo = new PPC64TargetCodeGenInfo(Types)); 4867 4868 case llvm::Triple::nvptx: 4869 case llvm::Triple::nvptx64: 4870 return *(TheTargetCodeGenInfo = new NVPTXTargetCodeGenInfo(Types)); 4871 4872 case llvm::Triple::mblaze: 4873 return *(TheTargetCodeGenInfo = new MBlazeTargetCodeGenInfo(Types)); 4874 4875 case llvm::Triple::msp430: 4876 return *(TheTargetCodeGenInfo = new MSP430TargetCodeGenInfo(Types)); 4877 4878 case llvm::Triple::tce: 4879 return *(TheTargetCodeGenInfo = new TCETargetCodeGenInfo(Types)); 4880 4881 case llvm::Triple::x86: { 4882 bool DisableMMX = strcmp(getContext().getTargetInfo().getABI(), "no-mmx") == 0; 4883 4884 if (Triple.isOSDarwin()) 4885 return *(TheTargetCodeGenInfo = 4886 new X86_32TargetCodeGenInfo(Types, true, true, DisableMMX, false, 4887 CodeGenOpts.NumRegisterParameters)); 4888 4889 switch (Triple.getOS()) { 4890 case llvm::Triple::Cygwin: 4891 case llvm::Triple::MinGW32: 4892 case llvm::Triple::AuroraUX: 4893 case llvm::Triple::DragonFly: 4894 case llvm::Triple::FreeBSD: 4895 case llvm::Triple::OpenBSD: 4896 case llvm::Triple::Bitrig: 4897 return *(TheTargetCodeGenInfo = 4898 new X86_32TargetCodeGenInfo(Types, false, true, DisableMMX, 4899 false, 4900 CodeGenOpts.NumRegisterParameters)); 4901 4902 case llvm::Triple::Win32: 4903 return *(TheTargetCodeGenInfo = 4904 new X86_32TargetCodeGenInfo(Types, false, true, DisableMMX, true, 4905 CodeGenOpts.NumRegisterParameters)); 4906 4907 default: 4908 return *(TheTargetCodeGenInfo = 4909 new X86_32TargetCodeGenInfo(Types, false, false, DisableMMX, 4910 false, 4911 CodeGenOpts.NumRegisterParameters)); 4912 } 4913 } 4914 4915 case llvm::Triple::x86_64: { 4916 bool HasAVX = strcmp(getContext().getTargetInfo().getABI(), "avx") == 0; 4917 4918 switch (Triple.getOS()) { 4919 case llvm::Triple::Win32: 4920 case llvm::Triple::MinGW32: 4921 case llvm::Triple::Cygwin: 4922 return *(TheTargetCodeGenInfo = new WinX86_64TargetCodeGenInfo(Types)); 4923 case llvm::Triple::NaCl: 4924 return *(TheTargetCodeGenInfo = new NaClX86_64TargetCodeGenInfo(Types, HasAVX)); 4925 default: 4926 return *(TheTargetCodeGenInfo = new X86_64TargetCodeGenInfo(Types, 4927 HasAVX)); 4928 } 4929 } 4930 case llvm::Triple::hexagon: 4931 return *(TheTargetCodeGenInfo = new HexagonTargetCodeGenInfo(Types)); 4932 } 4933 } 4934