| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 32 class SDNode;
579 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
580 SmallVectorImpl<SDNode*> &NewNodes) const {
601 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
614 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
[all...] |
| TargetLowering.h | 225 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
396 // If a target-specific SDNode requires legalization, require the target
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 181 std::pair<SDNode*, SDNode*>
182 MipsSEDAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty,
184 SDNode *Lo = 0, *Hi = 0;
185 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
201 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
203 SDNode *Node) const {
214 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops, 2);
215 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
302 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node)
[all...] |
| MipsISelLowering.h | 159 virtual void LowerOperationWrapper(SDNode *N,
169 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
179 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
226 const SDNode *CallNode,
233 bool IsSoftFloat, const SDNode *CallNode,
285 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
290 const SDNode *CallNode, const Type *RetTy) const;
310 const SDNode *CallNode, const Type *RetTy) const;
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 44 SDNode *Select(SDNode *N);
64 SDNode* getGlobalBaseReg();
68 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
137 SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
175 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 216 SDNode *N = SU->getNode();
237 SmallVector<SDNode*, 2> NewNodes;
245 SDNode *LoadNode = NewNodes[0];
391 SUnit *CopyFromSU = newSUnit(static_cast<SDNode *>(NULL));
395 SUnit *CopyToSU = newSUnit(static_cast<SDNode *>(NULL));
433 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
484 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
654 std::vector<SDNode*> Sequence;
655 DenseMap<SDNode*, SDNode*> GluedMap; // Cache glue to its use
[all...] |
| SelectionDAGISel.cpp | 264 SDNode *Node) const {
525 SmallPtrSet<SDNode*, 128> VisitedNodes;
526 SmallVector<SDNode*, 128> Worklist;
534 SDNode *N = Worklist.pop_back_val();
737 virtual void NodeDeleted(SDNode *N, SDNode *E) {
772 SDNode *Node = --ISelPosition;
779 SDNode *ResNode = Select(Node);
[all...] |
| LegalizeIntegerTypes.cpp | 35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
147 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
153 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
160 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
206 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
263 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
274 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
283 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
297 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
309 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N)
[all...] |
| LegalizeVectorTypes.cpp | 33 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
128 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
135 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
143 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
149 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
176 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
182 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
189 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N)
[all...] |
| LegalizeTypes.cpp | 73 SmallVector<SDNode*, 16> NewNodes;
88 for (SDNode::use_iterator UI = I->use_begin(), UE = I->use_end();
169 SDNode *N = NewNodes[i];
170 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
212 SDNode *N = Worklist.back();
321 SDNode *M = AnalyzeNewNode(N);
351 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
353 SDNode *User = *UI;
449 SDNode *DAGTypeLegalizer::AnalyzeNewNode(SDNode *N)
[all...] |
| DAGCombiner.cpp | 83 SmallPtrSet<SDNode*, 64> WorkListContents;
84 SmallVector<SDNode*, 64> WorkListOrder;
93 void AddUsersToWorkList(SDNode *N) {
94 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
101 SDValue visit(SDNode *N);
106 void AddToWorkList(SDNode *N) {
113 void removeFromWorkList(SDNode *N) {
117 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
120 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
124 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1
[all...] |
| LegalizeTypesGeneric.cpp | 33 void DAGTypeLegalizer::ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
39 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
182 void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
189 void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo,
201 void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo,
245 void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
287 void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
312 SDValue DAGTypeLegalizer::ExpandOp_BITCAST(SDNode *N) {
341 SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
375 SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N)
[all...] |
| InstrEmitter.cpp | 42 unsigned InstrEmitter::CountResults(SDNode *Node) {
58 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
84 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
109 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
111 SDNode *User = *UI;
190 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
195 SDNode *User = *Node->use_begin();
206 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
230 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
232 SDNode *User = *UI
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 90 SDNode *Select(SDNode *N);
93 bool hasNoVMLxHazardUse(SDNode *N) const;
135 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
137 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
139 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
144 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
148 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
149 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
176 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N
[all...] |
| ARMBaseInstrInfo.h | 153 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
164 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
229 SDNode *DefNode, unsigned DefIdx,
230 SDNode *UseNode, unsigned UseIdx) const;
274 SDNode *Node) const;
|
| ARMISelLowering.h | 262 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
280 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
282 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
283 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
321 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
329 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
380 Sched::Preference getSchedulingPreference(SDNode *N) const;
519 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
|
| /external/llvm/include/llvm/CodeGen/ |
| Analysis.h | 29 class SDNode;
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUInstrInfo.h | 105 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
106 SmallVectorImpl<SDNode *> &NewNodes) const;
110 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| R600ISelLowering.h | 30 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
31 void ReplaceNodeResults(SDNode * N,
|
| AMDGPUInstrInfo.cpp | 174 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
175 SmallVectorImpl<SDNode*> &NewNodes) const {
188 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 98 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
103 SDNode *getGlobalBaseReg();
107 SDNode *Select(SDNode *N);
109 SDNode *SelectBitfieldInsert(SDNode *N);
189 SDNode *SelectSETCC(SDNode *N);
261 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
287 static bool isIntS16Immediate(SDNode *N, short &Imm)
[all...] |
| PPCISelLowering.h | 300 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
309 bool isAllNegativeZeroVector(SDNode *N);
313 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
319 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
340 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
368 Sched::Preference getSchedulingPreference(SDNode *N) const;
377 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
380 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 302 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
303 SmallVectorImpl<SDNode*> &NewNodes) const;
320 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
331 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 95 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
161 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
162 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
164 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 95 SDNode* NVPTXDAGToDAGISel::Select(SDNode *N) {
100 SDNode *ResNode = NULL;
163 SDNode* NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
167 SDNode *NVPTXLD= NULL;
336 SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
343 SDNode *LD;
588 SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N)
[all...] |
