| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 143 const MCOperand &ImmOp = MI.getOperand(OpIdx);
220 const MCOperand &MO = MI.getOperand(OpIdx);
254 const MCOperand &MO = MI.getOperand(OpIdx);
289 const MCOperand &MO = MI.getOperand(OpIdx);
299 const MCOperand &MO = MI.getOperand(OpIdx);
310 const MCOperand &MO = MI.getOperand(OpIdx);
323 const MCOperand &MO = MI.getOperand(OpIdx);
361 const MCOperand &UImm16MO = MI.getOperand(OpIdx);
362 const MCOperand &ShiftMO = MI.getOperand(OpIdx + 1);
439 MCOperand UImm16MO = MI.getOperand(1)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 329 const MachineOperand &MO = MI->getOperand(OpNum);
371 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
403 const MachineOperand &MO = MI->getOperand(RegOp);
425 const MachineOperand &MO = MI->getOperand(OpNum);
434 const MachineOperand &MO = MI->getOperand(opNum);
506 const MachineOperand &MO = MI->getOperand(opNum);
537 const MachineOperand &MO = MI->getOperand(opNum);
580 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
582 return MachineLocation(MI->getOperand(0).getReg()
[all...] |
| MipsInstrInfo.cpp | 85 BB = Inst->getOperand(NumOp-1).getMBB();
89 Cond.push_back(Inst->getOperand(i));
233 TBB = LastInst->getOperand(0).getMBB();
256 TBB = SecondLastInst->getOperand(0).getMBB();
268 FBB = LastInst->getOperand(0).getMBB();
280 const char *AsmStr = MI->getOperand(0).getSymbolName();
|
| MipsISelLowering.cpp | 422 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
427 SDValue MultHi = ADDENode->getOperand(0);
428 SDValue MultLo = ADDCNode->getOperand(0);
462 MultNode->getOperand(0),// Factor 0
463 MultNode->getOperand(1),// Factor 1
464 ADDCNode->getOperand(1),// Lo0
465 ADDENode->getOperand(1));// Hi0
495 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
500 SDValue MultHi = SUBENode->getOperand(1);
501 SDValue MultLo = SUBCNode->getOperand(1)
[all...] |
| /external/llvm/include/llvm/IR/ |
| Instructions.h | 88 const Value *getArraySize() const { return getOperand(0); }
89 Value *getArraySize() { return getOperand(0); }
225 Value *getPointerOperand() { return getOperand(0); }
226 const Value *getPointerOperand() const { return getOperand(0); }
298 /// Transparently provide more efficient getOperand methods.
345 Value *getValueOperand() { return getOperand(0); }
346 const Value *getValueOperand() const { return getOperand(0); }
348 Value *getPointerOperand() { return getOperand(1); }
349 const Value *getPointerOperand() const { return getOperand(1); }
483 /// Transparently provide more efficient getOperand methods
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineCopyPropagation.cpp | 115 unsigned SrcSrc = CopyMI->getOperand(1).getReg();
119 unsigned SrcDef = CopyMI->getOperand(0).getReg();
151 unsigned Def = MI->getOperand(0).getReg();
152 unsigned Src = MI->getOperand(1).getReg();
237 MachineOperand &MO = MI->getOperand(i);
270 const MachineOperand &MaskMO = MI->getOperand(RegMaskOpNum);
274 unsigned Reg = (*DI)->getOperand(0).getReg();
312 if (!MRI->isReserved((*DI)->getOperand(0).getReg())) {
|
| PHIElimination.cpp | 155 unsigned DefReg = DefMI->getOperand(0).getReg();
212 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
227 unsigned DestReg = MPhi->getOperand(0).getReg();
228 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
229 bool isDead = MPhi->getOperand(0).isDead();
347 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
348 MPhi->getOperand(i).getReg())];
354 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
355 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
356 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() |
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 101 MI->getOperand(3).setIsDead();
164 MI->getOperand(3).setIsDead();
173 MI->getOperand(3).setIsDead();
238 uint64_t Amount = Old->getOperand(0).getImm();
253 uint64_t CalleeAmt = Old->getOperand(1).getImm();
263 New->getOperand(3).setIsDead();
272 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
278 New->getOperand(3).setIsDead();
|
| MSP430RegisterInfo.cpp | 115 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
129 Offset += MI.getOperand(FIOperandNum + 1).getImm();
137 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
143 unsigned DstReg = MI.getOperand(0).getReg();
154 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
155 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
| MSP430InstrInfo.cpp | 200 TBB = I->getOperand(0).getMBB();
211 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
219 TBB = I->getOperand(0).getMBB();
226 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
233 TBB = I->getOperand(0).getMBB();
245 if (TBB != I->getOperand(0).getMBB())
308 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
|
| MSP430ISelLowering.cpp | 631 if (!isa<ConstantSDNode>(N->getOperand(1)))
636 VT, N->getOperand(0), N->getOperand(1));
639 VT, N->getOperand(0), N->getOperand(1));
642 VT, N->getOperand(0), N->getOperand(1));
645 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
650 SDValue Victim = N->getOperand(0);
780 SDValue Chain = Op.getOperand(0)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | 608 unsigned CPI = CPEMI->getOperand(1).getIndex();
722 if (I->getOperand(op).isCPI()) {
777 unsigned CPI = I->getOperand(op).getIndex();
[all...] |
| Thumb2ITBlockPass.cpp | 62 MachineOperand &MO = MI->getOperand(i);
113 assert(MI->getOperand(0).getSubReg() == 0 &&
114 MI->getOperand(1).getSubReg() == 0 &&
117 unsigned DstReg = MI->getOperand(0).getReg();
118 unsigned SrcReg = MI->getOperand(1).getReg();
142 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
|
| ARMISelLowering.cpp | [all...] |
| ARMCodeEmitter.cpp | 157 return getMachineOpValue(MI, MI.getOperand(OpIdx));
261 const MachineOperand &MO = MI.getOperand(Op);
262 const MachineOperand &MO1 = MI.getOperand(Op + 1);
280 const MachineOperand &MO = MI.getOperand(Op);
316 const MachineOperand &MO = MI.getOperand(Op);
317 const MachineOperand &MO1 = MI.getOperand(Op + 1);
698 emitConstantToMemory(CPI, CA->getOperand(i));
707 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
708 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
742 const MachineOperand &MO0 = MI.getOperand(0)
[all...] |
| Thumb1RegisterInfo.cpp | 358 Offset += MI.getOperand(FrameRegIdx+1).getImm();
377 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
393 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
394 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset / Scale);
399 unsigned DestReg = MI.getOperand(0).getReg();
420 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
421 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
434 MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true);
435 MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
443 int InstrOffs = MI.getOperand(ImmIdx).getImm()
[all...] |
| /frameworks/compile/slang/BitWriter_2_9/ |
| BitcodeWriter.cpp | 587 if (N->getOperand(i)) {
588 Record.push_back(VE.getTypeID(N->getOperand(i)->getType()));
589 Record.push_back(VE.getValueID(N->getOperand(i)));
658 Record.push_back(VE.getValueID(NMD->getOperand(i)));
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 313 unsigned dest = MI->getOperand(0).getReg();
314 unsigned ptr = MI->getOperand(1).getReg();
315 unsigned incr = MI->getOperand(2).getReg();
397 unsigned dest = MI->getOperand(0).getReg();
398 unsigned ptr = MI->getOperand(1).getReg();
399 unsigned incr = MI->getOperand(2).getReg();
478 unsigned dest = MI->getOperand(0).getReg();
479 unsigned ptr = MI->getOperand(1).getReg();
480 unsigned oldval = MI->getOperand(2).getReg();
481 unsigned newval = MI->getOperand(3).getReg()
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolutionExpressions.h | 66 const SCEV *getOperand() const { return Op; }
148 const SCEV *getOperand(unsigned i) const {
157 Type *getType() const { return getOperand(0)->getType(); }
215 return getOperand(getNumOperands() - 1)->getType();
301 if (isAffine()) return getOperand(1);
516 push(cast<SCEVCastExpr>(S)->getOperand());
566 const SCEV *Operand = visit(Expr->getOperand());
571 const SCEV *Operand = visit(Expr->getOperand());
576 const SCEV *Operand = visit(Expr->getOperand());
583 Operands.push_back(visit(Expr->getOperand(i)))
[all...] |
| /external/llvm/lib/Linker/ |
| LinkModules.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 79 if (MI->getOperand(2).isFI() &&
80 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
81 FrameIndex = MI->getOperand(2).getIndex();
82 return MI->getOperand(0).getReg();
103 if (MI->getOperand(2).isFI() &&
104 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
105 FrameIndex = MI->getOperand(0).getIndex();
106 return MI->getOperand(2).getReg()
[all...] |
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 171 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
237 const MCOperand &MO = MI.getOperand(OpIdx);
251 MCOperand ImmOp = MI.getOperand(ImmOpIndex);
301 const MCOperand &RegMO = MI.getOperand(RegOpIdx);
302 const MCOperand &SelMO = MI.getOperand(SelOpIdx);
324 MCOperand ImmOp = MI.getOperand(ImmOpIndex);
344 int64_t Resource = MI.getOperand(OpOffset + 2).getImm();
345 int64_t Sampler = MI.getOperand(OpOffset + 3).getImm();
346 int64_t TextureType = MI.getOperand(OpOffset + 4).getImm();
359 EmitByte(getHWReg(MI.getOperand(1).getReg()), OS)
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 85 Value *CLHS = Cmp->getOperand(0), *CRHS = Cmp->getOperand(1);
140 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS;
163 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1);
205 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1);
206 Value *C = Op1->getOperand(0), *D = Op1->getOperand(1)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| SimplifyCFGPass.cpp | 152 Value *Ptr = SI->getOperand(1);
252 Ret->getOperand(0) != I))
269 Ret->getOperand(0) ==
270 cast<ReturnInst>(RetBlock->getTerminator())->getOperand(0)) {
279 Value *InVal = cast<ReturnInst>(RetBlock->getTerminator())->getOperand(0);
281 RetBlockPHI = PHINode::Create(Ret->getOperand(0)->getType(),
293 RetBlockPHI->addIncoming(Ret->getOperand(0), &BB);
|
| CodeGenPrepare.cpp | 461 EVT SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
516 CastInst::Create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "",
573 CI->getPredicate(), CI->getOperand(0),
574 CI->getOperand(1), "", InsertPt);
719 V = BCI->getOperand(0);
[all...] |
