| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 145 SDValue N0 = N.getOperand(0);
211 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
212 !MatchAddress(N.getNode()->getOperand(1), AM))
215 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
216 !MatchAddress(N.getNode()->getOperand(0), AM))
225 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
229 if (!MatchAddress(N.getOperand(0), AM) &&
233 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
421 Node->getOperand(0), Node->getOperand(1)
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 34 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo));
160 ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1);
161 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1);
168 return I->getOperand(0);
171 return I->getOperand(1);
182 ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1);
183 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1);
190 return I->getOperand(0);
193 return I->getOperand(1);
199 return I->getOperand(0)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 78 const MachineOperand &MO = OldMI.getOperand(i);
387 bool DstIsDead = MI.getOperand(OpIdx).isDead();
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++));
418 MIB.addOperand(MI.getOperand(OpIdx++));
423 MachineOperand MO = MI.getOperand(SrcOpIdx)
[all...] |
| ARMAsmPrinter.cpp | 221 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
222 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
336 const MachineOperand &MO = MI->getOperand(OpNum);
428 if (MI->getOperand(OpNum).isReg()) {
430 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
436 if (!MI->getOperand(OpNum).isImm())
438 O << MI->getOperand(OpNum).getImm();
445 if (MI->getOperand(OpNum).isReg())
[all...] |
| ARMBaseInstrInfo.cpp | 155 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
156 const MachineOperand &Base = MI->getOperand(2);
157 const MachineOperand &Offset = MI->getOperand(NumOps-3);
161 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
213 get(MemOpc), MI->getOperand(0).getReg())
217 get(MemOpc)).addReg(MI->getOperand(1).getReg())
224 get(MemOpc), MI->getOperand(0).getReg())
228 get(MemOpc)).addReg(MI->getOperand(1).getReg()
[all...] |
| A15SDOptimizer.cpp | 171 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
173 SReg = MI->getOperand(1).getReg();
199 MachineOperand &MO = MI->getOperand(i);
222 MachineOperand &MODef = Def->getOperand(j);
255 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
259 unsigned DPRReg = MI->getOperand(1).getReg();
260 unsigned SPRReg = MI->getOperand(2).getReg();
263 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
264 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
276 EC->getOperand(1).getSubReg() == ARM::ssub_0)
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86IntelInstPrinter.cpp | 54 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
78 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
120 const MCOperand &Op = MI->getOperand(OpNo);
147 const MCOperand &Op = MI->getOperand(OpNo);
160 const MCOperand &BaseReg = MI->getOperand(Op);
161 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
162 const MCOperand &IndexReg = MI->getOperand(Op+2);
163 const MCOperand &DispSpec = MI->getOperand(Op+3);
164 const MCOperand &SegReg = MI->getOperand(Op+4);
|
| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 71 MachineOperand &MO = MI->getOperand(i);
80 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
81 MI->getOperand(1).isImm() &&
82 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
83 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
85 unsigned DstReg = MI->getOperand(0).getReg();
86 unsigned InsReg = MI->getOperand(2).getReg();
87 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?")
[all...] |
| OptimizePHIs.cpp | 87 unsigned DstReg = MI->getOperand(0).getReg();
99 unsigned SrcReg = MI->getOperand(i).getReg();
106 !SrcMI->getOperand(0).getSubReg() &&
107 !SrcMI->getOperand(1).getSubReg() &&
108 TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
109 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
130 unsigned DstReg = MI->getOperand(0).getReg();
167 unsigned OldReg = MI->getOperand(0).getReg();
|
| TargetInstrInfo.cpp | 122 if (HasDef && !MI->getOperand(0).isReg())
133 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
135 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
136 unsigned Reg1 = MI->getOperand(Idx1).getReg();
137 unsigned Reg2 = MI->getOperand(Idx2).getReg();
138 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
139 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
140 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
141 bool Reg1IsKill = MI->getOperand(Idx1).isKill()
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 88 SrcReg = MI.getOperand(1).getReg();
89 DstReg = MI.getOperand(0).getReg();
103 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104 MI->getOperand(2).isFI()) {
105 FrameIndex = MI->getOperand(2).getIndex();
106 return MI->getOperand(0).getReg();
121 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122 MI->getOperand(2).isFI())
[all...] |
| PPCISelDAGToDAG.cpp | 335 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
371 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
404 SDValue Op0 = N->getOperand(0);
405 SDValue Op1 = N->getOperand(1);
425 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
426 Op0.getOperand(0).getOpcode() == ISD::SRL) {
427 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
428 Op1.getOperand(0).getOpcode() != ISD::SRL) {
435 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
436 Op1.getOperand(0).getOpcode() != ISD::SRL)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 426 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
430 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
444 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
448 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
454 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
464 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
482 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
486 GetNegatedExpression(Op.getOperand(0), DAG,
488 Op.getOperand(1));
491 GetNegatedExpression(Op.getOperand(1), DAG
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 67 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
72 MI.getOperand(FIOperandNum + 1).getImm();
78 MI.getOperand(FIOperandNum).ChangeToRegister(SP::I6, false);
79 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
89 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
90 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
|
| SparcAsmPrinter.cpp | 74 const MachineOperand &MO = MI->getOperand (opNum);
122 if (MI->getOperand(opNum+1).isReg() &&
123 MI->getOperand(opNum+1).getReg() == SP::G0)
125 if (MI->getOperand(opNum+1).isImm() &&
126 MI->getOperand(opNum+1).getImm() == 0)
130 if (MI->getOperand(opNum+1).isGlobal() ||
131 MI->getOperand(opNum+1).isCPI()) {
143 const MachineOperand &MO = MI->getOperand(opNum);
176 int CC = (int)MI->getOperand(opNum).getImm();
251 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 46 if ((MI->getOperand(1).isFI()) && // is a stack slot
47 (MI->getOperand(2).isImm()) && // the imm is zero
48 (isZeroImm(MI->getOperand(2)))) {
49 FrameIndex = MI->getOperand(1).getIndex();
50 return MI->getOperand(0).getReg();
65 if ((MI->getOperand(1).isFI()) && // is a stack slot
66 (MI->getOperand(2).isImm()) && // the imm is zero
67 (isZeroImm(MI->getOperand(2)))) {
68 FrameIndex = MI->getOperand(1).getIndex();
69 return MI->getOperand(0).getReg()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 43 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
44 N->getOperand(1));
168 Base = Addr.getOperand(0);
169 Offset = Addr.getOperand(1);
179 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
184 (Addr.getOperand(0))) {
189 Base = Addr.getOperand(0);
205 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
206 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
207 SDValue Opnd0 = Addr.getOperand(1).getOperand(0)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUIndirectAddressing.cpp | 96 unsigned RegIndex = MI.getOperand(2).getImm();
97 unsigned Channel = MI.getOperand(3).getImm();
100 TII->getIndirectAddrStoreRegClass(MI.getOperand(0).getReg());
102 if (MI.getOperand(1).getReg() == AMDGPU::INDIRECT_BASE_ADDR) {
107 .addOperand(MI.getOperand(0));
114 MI.getOperand(0).getReg(), // Value
116 MI.getOperand(1).getReg()); // Offset
220 MachineOperand &MO = MI.getOperand(OpIdx);
246 unsigned RegIndex = MI.getOperand(2).getImm();
247 unsigned Channel = MI.getOperand(3).getImm()
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 61 if ((MI->getOperand(1).isFI()) && // is a stack slot
62 (MI->getOperand(2).isImm()) && // the imm is zero
63 (isZeroImm(MI->getOperand(2))))
65 FrameIndex = MI->getOperand(1).getIndex();
66 return MI->getOperand(0).getReg();
83 if ((MI->getOperand(1).isFI()) && // is a stack slot
84 (MI->getOperand(2).isImm()) && // the imm is zero
85 (isZeroImm(MI->getOperand(2))))
87 FrameIndex = MI->getOperand(1).getIndex();
88 return MI->getOperand(0).getReg()
[all...] |
| /external/llvm/lib/Target/Hexagon/InstPrinter/ |
| HexagonInstPrinter.cpp | 91 const MCOperand& MO = MI->getOperand(OpNo);
106 const MCOperand& MO = MI->getOperand(OpNo);
111 O << MI->getOperand(OpNo).getImm();
127 O << MI->getOperand(OpNo).getImm();
132 O << -MI->getOperand(OpNo).getImm();
142 const MCOperand& MO0 = MI->getOperand(OpNo);
143 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
151 const MCOperand& MO0 = MI->getOperand(OpNo);
152 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
159 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression")
[all...] |
| /external/llvm/lib/Analysis/ |
| PHITransAddr.cpp | 35 isa<ConstantInt>(Inst->getOperand(1)))
40 // cerr << "OP:\t\t\t\t" << *PtrInst->getOperand(0);
83 if (!VerifySubExpr(I->getOperand(i), InstInputs))
140 if (Instruction *Op = dyn_cast<Instruction>(I->getOperand(i)))
181 if (Instruction *Op = dyn_cast<Instruction>(Inst->getOperand(i)))
191 Value *PHIIn = PHITranslateSubExpr(Cast->getOperand(0), CurBB, PredBB, DT);
193 if (PHIIn == Cast->getOperand(0))
221 Value *GEPOp = PHITranslateSubExpr(GEP->getOperand(i), CurBB, PredBB, DT);
224 AnyChanged |= GEPOp != GEP->getOperand(i);
250 if (GEPI->getOperand(i) != GEPOps[i])
[all...] |
| /external/llvm/include/llvm/IR/ |
| GlobalAlias.h | 62 return getOperand(0);
65 return getOperand(0);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.cpp | 129 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
133 MI.getOperand(FIOperandNum+1).getImm();
136 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
137 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
|
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyIndVar.cpp | 100 if (IVOperand != UseInst->getOperand(OperIdx) ||
101 !isa<ConstantInt>(UseInst->getOperand(1)))
107 || !isa<ConstantInt>(IVOperand->getOperand(1)))
110 IVSrc = IVOperand->getOperand(0);
114 ConstantInt *D = cast<ConstantInt>(UseInst->getOperand(1));
152 if (IVOperand != ICmp->getOperand(0)) {
154 assert(IVOperand == ICmp->getOperand(1) && "Can't find IVOperand");
160 const SCEV *S = SE->getSCEV(ICmp->getOperand(IVOperIdx));
161 const SCEV *X = SE->getSCEV(ICmp->getOperand(1 - IVOperIdx));
190 if (IVOperand != Rem->getOperand(0)
[all...] |
