Lines Matching full:x86
1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
61 return X86::SUB64ri8;
62 return X86::SUB64ri32;
65 return X86::SUB32ri8;
66 return X86::SUB32ri;
73 return X86::ADD64ri8;
74 return X86::ADD64ri32;
77 return X86::ADD32ri8;
78 return X86::ADD32ri;
83 return IsLP64 ? X86::LEA64r : X86::LEA32r;
99 X86::EAX, X86::EDX, X86::ECX, 0
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
110 case X86::RET:
111 case X86::RETI:
112 case X86::TCRETURNdi:
113 case X86::TCRETURNri:
114 case X86::TCRETURNmi:
115 case X86::TCRETURNdi64:
116 case X86::TCRETURNri64:
117 case X86::TCRETURNmi64:
118 case X86::EH_RETURN:
119 case X86::EH_RETURN64: {
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL)
373 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
376 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
499 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
501 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
517 if (Opc == X86::PROLOG_LABEL) continue;
528 if (Reg == (Is64Bit ? X86::RAX : X86::EAX)) {
547 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
548 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
633 for (MachineRegisterInfo::reg_iterator ri = MRI.reg_begin(X86::EFLAGS),
687 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
755 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
762 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
778 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
785 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
807 (MBBI->getOpcode() == X86::PUSH32r ||
808 MBBI->getOpcode() == X86::PUSH64r)) {
816 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
838 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
891 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
892 .addReg(X86::EAX, RegState::Kill)
899 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
905 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
911 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
914 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
920 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), StackPtr)
922 .addReg(X86::RAX)
928 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
929 X86::EAX),
944 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
953 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
995 case X86::RET:
996 case X86::RETI:
997 case X86::TCRETURNdi:
998 case X86::TCRETURNri:
999 case X86::TCRETURNmi:
1000 case X86::TCRETURNdi64:
1001 case X86::TCRETURNri64:
1002 case X86::TCRETURNmi64:
1003 case X86::EH_RETURN:
1004 case X86::EH_RETURN64:
1039 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1049 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1075 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1086 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1091 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1093 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1094 RetOpcode == X86::TCRETURNmi ||
1095 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1096 RetOpcode == X86::TCRETURNmi64) {
1097 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1122 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1124 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1125 ? X86::TAILJMPd : X86::TAILJMPd64));
1134 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1136 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1137 ? X86::TAILJMPm : X86::TAILJMPm64));
1140 } else if (RetOpcode == X86::TCRETURNri64) {
1141 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1144 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1153 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1243 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1246 if (!X86::GR64RegClass.contains(Reg) &&
1247 !X86::GR32RegClass.contains(Reg))
1261 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1266 if (X86::GR64RegClass.contains(Reg) ||
1267 X86::GR32RegClass.contains(Reg))
1294 if (X86::GR64RegClass.contains(Reg) ||
1295 X86::GR32RegClass.contains(Reg))
1304 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1307 if (!X86::GR64RegClass.contains(Reg) &&
1308 !X86::GR32RegClass.contains(Reg))
1385 return Primary ? X86::R14 : X86::R13;
1387 return Primary ? X86::EBX : X86::EDI;
1391 return Primary ? X86::R11 : X86::R12;
1400 return Primary ? X86::EAX : X86::ECX;
1403 return Primary ? X86::EDX : X86::EAX;
1404 return Primary ? X86::ECX : X86::EAX;
1450 allocMBB->addLiveIn(X86::R10);
1467 TlsReg = X86::FS;
1470 TlsReg = X86::GS;
1473 TlsReg = X86::FS;
1480 ScratchReg = X86::RSP;
1482 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1485 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1489 TlsReg = X86::GS;
1492 TlsReg = X86::GS;
1495 TlsReg = X86::FS;
1504 ScratchReg = X86::ESP;
1506 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1510 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1534 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1537 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1539 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1546 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1552 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1561 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1563 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1565 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1567 MF.getRegInfo().setPhysRegUsed(X86::R10);
1568 MF.getRegInfo().setPhysRegUsed(X86::R11);
1570 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1572 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1578 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1581 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1585 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1587 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1697 SPReg = X86::RSP;
1698 PReg = X86::RBP;
1699 LEAop = X86::LEA64r;
1700 CMPop = X86::CMP64rm;
1701 CALLop = X86::CALL64pcrel32;
1704 SPReg = X86::ESP;
1705 PReg = X86::EBP;
1706 LEAop = X86::LEA32r;
1707 CMPop = X86::CMP32rm;
1708 CALLop = X86::CALLpcrel32;
1722 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1731 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
