1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements integer type expansion and promotion for LegalizeTypes. 11 // Promotion is the act of changing a computation in an illegal type into a 12 // computation in a larger type. For example, implementing i8 arithmetic in an 13 // i32 register (often needed on powerpc). 14 // Expansion is the act of changing a computation in an illegal type into a 15 // computation in two identical registers of a smaller type. For example, 16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17 // targets). 18 // 19 //===----------------------------------------------------------------------===// 20 21 #include "LegalizeTypes.h" 22 #include "llvm/IR/DerivedTypes.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/raw_ostream.h" 25 using namespace llvm; 26 27 //===----------------------------------------------------------------------===// 28 // Integer Result Promotion 29 //===----------------------------------------------------------------------===// 30 31 /// PromoteIntegerResult - This method is called when a result of a node is 32 /// found to be in need of promotion to a larger type. At this point, the node 33 /// may also have invalid operands or may have other results that need 34 /// expansion, we just know that (at least) one result needs promotion. 35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n"); 37 SDValue Res = SDValue(); 38 39 // See if the target wants to custom expand this node. 40 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 41 return; 42 43 switch (N->getOpcode()) { 44 default: 45 #ifndef NDEBUG 46 dbgs() << "PromoteIntegerResult #" << ResNo << ": "; 47 N->dump(&DAG); dbgs() << "\n"; 48 #endif 49 llvm_unreachable("Do not know how to promote this operator!"); 50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; 51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 57 case ISD::CONVERT_RNDSAT: 58 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 59 case ISD::CTLZ_ZERO_UNDEF: 60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 61 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 62 case ISD::CTTZ_ZERO_UNDEF: 63 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 64 case ISD::EXTRACT_VECTOR_ELT: 65 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 66 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 67 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 68 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; 69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 72 case ISD::SIGN_EXTEND_INREG: 73 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 76 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 77 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 78 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 79 80 case ISD::EXTRACT_SUBVECTOR: 81 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break; 82 case ISD::VECTOR_SHUFFLE: 83 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break; 84 case ISD::INSERT_VECTOR_ELT: 85 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break; 86 case ISD::BUILD_VECTOR: 87 Res = PromoteIntRes_BUILD_VECTOR(N); break; 88 case ISD::SCALAR_TO_VECTOR: 89 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break; 90 case ISD::CONCAT_VECTORS: 91 Res = PromoteIntRes_CONCAT_VECTORS(N); break; 92 93 case ISD::SIGN_EXTEND: 94 case ISD::ZERO_EXTEND: 95 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 96 97 case ISD::FP_TO_SINT: 98 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 99 100 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break; 101 102 case ISD::AND: 103 case ISD::OR: 104 case ISD::XOR: 105 case ISD::ADD: 106 case ISD::SUB: 107 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 108 109 case ISD::SDIV: 110 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 111 112 case ISD::UDIV: 113 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 114 115 case ISD::SADDO: 116 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 117 case ISD::UADDO: 118 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 119 case ISD::SMULO: 120 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 121 122 case ISD::ATOMIC_LOAD: 123 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break; 124 125 case ISD::ATOMIC_LOAD_ADD: 126 case ISD::ATOMIC_LOAD_SUB: 127 case ISD::ATOMIC_LOAD_AND: 128 case ISD::ATOMIC_LOAD_OR: 129 case ISD::ATOMIC_LOAD_XOR: 130 case ISD::ATOMIC_LOAD_NAND: 131 case ISD::ATOMIC_LOAD_MIN: 132 case ISD::ATOMIC_LOAD_MAX: 133 case ISD::ATOMIC_LOAD_UMIN: 134 case ISD::ATOMIC_LOAD_UMAX: 135 case ISD::ATOMIC_SWAP: 136 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 137 138 case ISD::ATOMIC_CMP_SWAP: 139 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 140 } 141 142 // If the result is null then the sub-method took care of registering it. 143 if (Res.getNode()) 144 SetPromotedInteger(SDValue(N, ResNo), Res); 145 } 146 147 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N, 148 unsigned ResNo) { 149 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 150 return GetPromotedInteger(Op); 151 } 152 153 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 154 // Sign-extend the new bits, and continue the assertion. 155 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 156 return DAG.getNode(ISD::AssertSext, SDLoc(N), 157 Op.getValueType(), Op, N->getOperand(1)); 158 } 159 160 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 161 // Zero the new bits, and continue the assertion. 162 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 163 return DAG.getNode(ISD::AssertZext, SDLoc(N), 164 Op.getValueType(), Op, N->getOperand(1)); 165 } 166 167 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) { 168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 169 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), 170 N->getMemoryVT(), ResVT, 171 N->getChain(), N->getBasePtr(), 172 N->getMemOperand(), N->getOrdering(), 173 N->getSynchScope()); 174 // Legalized the chain result - switch anything that used the old chain to 175 // use the new one. 176 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 177 return Res; 178 } 179 180 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 181 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 182 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), 183 N->getMemoryVT(), 184 N->getChain(), N->getBasePtr(), 185 Op2, N->getMemOperand(), N->getOrdering(), 186 N->getSynchScope()); 187 // Legalized the chain result - switch anything that used the old chain to 188 // use the new one. 189 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 190 return Res; 191 } 192 193 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 194 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 195 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 196 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), 197 N->getMemoryVT(), N->getChain(), N->getBasePtr(), 198 Op2, Op3, N->getMemOperand(), N->getOrdering(), 199 N->getSynchScope()); 200 // Legalized the chain result - switch anything that used the old chain to 201 // use the new one. 202 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 203 return Res; 204 } 205 206 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) { 207 SDValue InOp = N->getOperand(0); 208 EVT InVT = InOp.getValueType(); 209 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 210 EVT OutVT = N->getValueType(0); 211 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 212 SDLoc dl(N); 213 214 switch (getTypeAction(InVT)) { 215 case TargetLowering::TypeLegal: 216 break; 217 case TargetLowering::TypePromoteInteger: 218 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector()) 219 // The input promotes to the same size. Convert the promoted value. 220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); 221 break; 222 case TargetLowering::TypeSoftenFloat: 223 // Promote the integer operand by hand. 224 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 225 case TargetLowering::TypeExpandInteger: 226 case TargetLowering::TypeExpandFloat: 227 break; 228 case TargetLowering::TypeScalarizeVector: 229 // Convert the element to an integer and promote it by hand. 230 if (!NOutVT.isVector()) 231 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 232 BitConvertToInteger(GetScalarizedVector(InOp))); 233 break; 234 case TargetLowering::TypeSplitVector: { 235 // For example, i32 = BITCAST v2i16 on alpha. Convert the split 236 // pieces of the input into integers and reassemble in the final type. 237 SDValue Lo, Hi; 238 GetSplitVector(N->getOperand(0), Lo, Hi); 239 Lo = BitConvertToInteger(Lo); 240 Hi = BitConvertToInteger(Hi); 241 242 if (TLI.isBigEndian()) 243 std::swap(Lo, Hi); 244 245 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 246 EVT::getIntegerVT(*DAG.getContext(), 247 NOutVT.getSizeInBits()), 248 JoinIntegers(Lo, Hi)); 249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); 250 } 251 case TargetLowering::TypeWidenVector: 252 // The input is widened to the same size. Convert to the widened value. 253 // Make sure that the outgoing value is not a vector, because this would 254 // make us bitcast between two vectors which are legalized in different ways. 255 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) 256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); 257 } 258 259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 260 CreateStackStoreLoad(InOp, OutVT)); 261 } 262 263 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 264 SDValue Op = GetPromotedInteger(N->getOperand(0)); 265 EVT OVT = N->getValueType(0); 266 EVT NVT = Op.getValueType(); 267 SDLoc dl(N); 268 269 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 271 DAG.getConstant(DiffBits, TLI.getPointerTy())); 272 } 273 274 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 275 // The pair element type may be legal, or may not promote to the same type as 276 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 277 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), 278 TLI.getTypeToTransformTo(*DAG.getContext(), 279 N->getValueType(0)), JoinIntegers(N->getOperand(0), 280 N->getOperand(1))); 281 } 282 283 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 284 EVT VT = N->getValueType(0); 285 // FIXME there is no actual debug info here 286 SDLoc dl(N); 287 // Zero extend things like i1, sign extend everything else. It shouldn't 288 // matter in theory which one we pick, but this tends to give better code? 289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 290 SDValue Result = DAG.getNode(Opc, dl, 291 TLI.getTypeToTransformTo(*DAG.getContext(), VT), 292 SDValue(N, 0)); 293 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 294 return Result; 295 } 296 297 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 298 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 299 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 300 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 301 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 302 "can only promote integers"); 303 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 304 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0), 305 N->getOperand(1), N->getOperand(2), 306 N->getOperand(3), N->getOperand(4), CvtCode); 307 } 308 309 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 310 // Zero extend to the promoted type and do the count there. 311 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 312 SDLoc dl(N); 313 EVT OVT = N->getValueType(0); 314 EVT NVT = Op.getValueType(); 315 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op); 316 // Subtract off the extra leading bits in the bigger type. 317 return DAG.getNode(ISD::SUB, dl, NVT, Op, 318 DAG.getConstant(NVT.getSizeInBits() - 319 OVT.getSizeInBits(), NVT)); 320 } 321 322 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 323 // Zero extend to the promoted type and do the count there. 324 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 325 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op); 326 } 327 328 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 329 SDValue Op = GetPromotedInteger(N->getOperand(0)); 330 EVT OVT = N->getValueType(0); 331 EVT NVT = Op.getValueType(); 332 SDLoc dl(N); 333 if (N->getOpcode() == ISD::CTTZ) { 334 // The count is the same in the promoted type except if the original 335 // value was zero. This can be handled by setting the bit just off 336 // the top of the original type. 337 APInt TopBit(NVT.getSizeInBits(), 0); 338 TopBit.setBit(OVT.getSizeInBits()); 339 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 340 } 341 return DAG.getNode(N->getOpcode(), dl, NVT, Op); 342 } 343 344 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 345 SDLoc dl(N); 346 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), 348 N->getOperand(1)); 349 } 350 351 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 352 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 353 unsigned NewOpc = N->getOpcode(); 354 SDLoc dl(N); 355 356 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 357 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT 358 // and SINT conversions are Custom, there is no way to tell which is 359 // preferable. We choose SINT because that's the right thing on PPC.) 360 if (N->getOpcode() == ISD::FP_TO_UINT && 361 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 362 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 363 NewOpc = ISD::FP_TO_SINT; 364 365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 366 367 // Assert that the converted value fits in the original type. If it doesn't 368 // (eg: because the value being converted is too big), then the result of the 369 // original operation was undefined anyway, so the assert is still correct. 370 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 371 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, 372 DAG.getValueType(N->getValueType(0).getScalarType())); 373 } 374 375 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) { 376 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 377 SDLoc dl(N); 378 379 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 380 381 return DAG.getNode(ISD::AssertZext, dl, 382 NVT, Res, DAG.getValueType(N->getValueType(0))); 383 } 384 385 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 387 SDLoc dl(N); 388 389 if (getTypeAction(N->getOperand(0).getValueType()) 390 == TargetLowering::TypePromoteInteger) { 391 SDValue Res = GetPromotedInteger(N->getOperand(0)); 392 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 393 394 // If the result and operand types are the same after promotion, simplify 395 // to an in-register extension. 396 if (NVT == Res.getValueType()) { 397 // The high bits are not guaranteed to be anything. Insert an extend. 398 if (N->getOpcode() == ISD::SIGN_EXTEND) 399 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 400 DAG.getValueType(N->getOperand(0).getValueType())); 401 if (N->getOpcode() == ISD::ZERO_EXTEND) 402 return DAG.getZeroExtendInReg(Res, dl, 403 N->getOperand(0).getValueType().getScalarType()); 404 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 405 return Res; 406 } 407 } 408 409 // Otherwise, just extend the original operand all the way to the larger type. 410 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 411 } 412 413 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 414 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 416 ISD::LoadExtType ExtType = 417 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 418 SDLoc dl(N); 419 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 420 N->getPointerInfo(), 421 N->getMemoryVT(), N->isVolatile(), 422 N->isNonTemporal(), N->getAlignment()); 423 424 // Legalized the chain result - switch anything that used the old chain to 425 // use the new one. 426 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 427 return Res; 428 } 429 430 /// Promote the overflow flag of an overflowing arithmetic node. 431 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 432 // Simply change the return type of the boolean result. 433 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); 434 EVT ValueVTs[] = { N->getValueType(0), NVT }; 435 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 436 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), 437 DAG.getVTList(ValueVTs, 2), Ops, 2); 438 439 // Modified the sum result - switch anything that used the old sum to use 440 // the new one. 441 ReplaceValueWith(SDValue(N, 0), Res); 442 443 return SDValue(Res.getNode(), 1); 444 } 445 446 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 447 if (ResNo == 1) 448 return PromoteIntRes_Overflow(N); 449 450 // The operation overflowed iff the result in the larger type is not the 451 // sign extension of its truncation to the original type. 452 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 453 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 454 EVT OVT = N->getOperand(0).getValueType(); 455 EVT NVT = LHS.getValueType(); 456 SDLoc dl(N); 457 458 // Do the arithmetic in the larger type. 459 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 460 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 461 462 // Calculate the overflow flag: sign extend the arithmetic result from 463 // the original type. 464 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 465 DAG.getValueType(OVT)); 466 // Overflowed if and only if this is not equal to Res. 467 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 468 469 // Use the calculated overflow everywhere. 470 ReplaceValueWith(SDValue(N, 1), Ofl); 471 472 return Res; 473 } 474 475 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 476 // Sign extend the input. 477 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 478 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 479 return DAG.getNode(N->getOpcode(), SDLoc(N), 480 LHS.getValueType(), LHS, RHS); 481 } 482 483 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 484 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 485 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 486 return DAG.getSelect(SDLoc(N), 487 LHS.getValueType(), N->getOperand(0), LHS, RHS); 488 } 489 490 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) { 491 SDValue Mask = N->getOperand(0); 492 EVT OpTy = N->getOperand(1).getValueType(); 493 494 // Promote all the way up to the canonical SetCC type. 495 Mask = PromoteTargetBoolean(Mask, getSetCCResultType(OpTy)); 496 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 497 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 498 return DAG.getNode(ISD::VSELECT, SDLoc(N), 499 LHS.getValueType(), Mask, LHS, RHS); 500 } 501 502 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 503 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 504 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 505 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), 506 LHS.getValueType(), N->getOperand(0), 507 N->getOperand(1), LHS, RHS, N->getOperand(4)); 508 } 509 510 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 511 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType()); 512 513 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 514 515 // Only use the result of getSetCCResultType if it is legal, 516 // otherwise just use the promoted result type (NVT). 517 if (!TLI.isTypeLegal(SVT)) 518 SVT = NVT; 519 520 SDLoc dl(N); 521 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() && 522 "Vector compare must return a vector result!"); 523 524 SDValue LHS = N->getOperand(0); 525 SDValue RHS = N->getOperand(1); 526 if (LHS.getValueType() != RHS.getValueType()) { 527 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger && 528 !LHS.getValueType().isVector()) 529 LHS = GetPromotedInteger(LHS); 530 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger && 531 !RHS.getValueType().isVector()) 532 RHS = GetPromotedInteger(RHS); 533 } 534 535 // Get the SETCC result using the canonical SETCC type. 536 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS, 537 N->getOperand(2)); 538 539 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 540 // Convert to the expected type. 541 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 542 } 543 544 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 545 SDValue Res = GetPromotedInteger(N->getOperand(0)); 546 SDValue Amt = N->getOperand(1); 547 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt; 548 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt); 549 } 550 551 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 552 SDValue Op = GetPromotedInteger(N->getOperand(0)); 553 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), 554 Op.getValueType(), Op, N->getOperand(1)); 555 } 556 557 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 558 // The input may have strange things in the top bits of the registers, but 559 // these operations don't care. They may have weird bits going out, but 560 // that too is okay if they are integer operations. 561 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 562 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 563 return DAG.getNode(N->getOpcode(), SDLoc(N), 564 LHS.getValueType(), LHS, RHS); 565 } 566 567 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 568 // The input value must be properly sign extended. 569 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 570 SDValue Amt = N->getOperand(1); 571 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt; 572 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt); 573 } 574 575 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 576 // The input value must be properly zero extended. 577 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 578 SDValue Amt = N->getOperand(1); 579 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt; 580 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt); 581 } 582 583 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 584 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 585 SDValue Res; 586 SDValue InOp = N->getOperand(0); 587 SDLoc dl(N); 588 589 switch (getTypeAction(InOp.getValueType())) { 590 default: llvm_unreachable("Unknown type action!"); 591 case TargetLowering::TypeLegal: 592 case TargetLowering::TypeExpandInteger: 593 Res = InOp; 594 break; 595 case TargetLowering::TypePromoteInteger: 596 Res = GetPromotedInteger(InOp); 597 break; 598 case TargetLowering::TypeSplitVector: 599 EVT InVT = InOp.getValueType(); 600 assert(InVT.isVector() && "Cannot split scalar types"); 601 unsigned NumElts = InVT.getVectorNumElements(); 602 assert(NumElts == NVT.getVectorNumElements() && 603 "Dst and Src must have the same number of elements"); 604 assert(isPowerOf2_32(NumElts) && 605 "Promoted vector type must be a power of two"); 606 607 SDValue EOp1, EOp2; 608 GetSplitVector(InOp, EOp1, EOp2); 609 610 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(), 611 NumElts/2); 612 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1); 613 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2); 614 615 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); 616 } 617 618 // Truncate to NVT instead of VT 619 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res); 620 } 621 622 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 623 if (ResNo == 1) 624 return PromoteIntRes_Overflow(N); 625 626 // The operation overflowed iff the result in the larger type is not the 627 // zero extension of its truncation to the original type. 628 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 629 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 630 EVT OVT = N->getOperand(0).getValueType(); 631 EVT NVT = LHS.getValueType(); 632 SDLoc dl(N); 633 634 // Do the arithmetic in the larger type. 635 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 636 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 637 638 // Calculate the overflow flag: zero extend the arithmetic result from 639 // the original type. 640 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); 641 // Overflowed if and only if this is not equal to Res. 642 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 643 644 // Use the calculated overflow everywhere. 645 ReplaceValueWith(SDValue(N, 1), Ofl); 646 647 return Res; 648 } 649 650 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 651 // Promote the overflow bit trivially. 652 if (ResNo == 1) 653 return PromoteIntRes_Overflow(N); 654 655 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1); 656 SDLoc DL(N); 657 EVT SmallVT = LHS.getValueType(); 658 659 // To determine if the result overflowed in a larger type, we extend the 660 // input to the larger type, do the multiply (checking if it overflows), 661 // then also check the high bits of the result to see if overflow happened 662 // there. 663 if (N->getOpcode() == ISD::SMULO) { 664 LHS = SExtPromotedInteger(LHS); 665 RHS = SExtPromotedInteger(RHS); 666 } else { 667 LHS = ZExtPromotedInteger(LHS); 668 RHS = ZExtPromotedInteger(RHS); 669 } 670 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1)); 671 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS); 672 673 // Overflow occurred if it occurred in the larger type, or if the high part 674 // of the result does not zero/sign-extend the low part. Check this second 675 // possibility first. 676 SDValue Overflow; 677 if (N->getOpcode() == ISD::UMULO) { 678 // Unsigned overflow occurred if the high part is non-zero. 679 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, 680 DAG.getIntPtrConstant(SmallVT.getSizeInBits())); 681 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi, 682 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE); 683 } else { 684 // Signed overflow occurred if the high part does not sign extend the low. 685 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), 686 Mul, DAG.getValueType(SmallVT)); 687 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); 688 } 689 690 // The only other way for overflow to occur is if the multiplication in the 691 // larger type itself overflowed. 692 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow, 693 SDValue(Mul.getNode(), 1)); 694 695 // Use the calculated overflow everywhere. 696 ReplaceValueWith(SDValue(N, 1), Overflow); 697 return Mul; 698 } 699 700 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 701 // Zero extend the input. 702 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 703 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 704 return DAG.getNode(N->getOpcode(), SDLoc(N), 705 LHS.getValueType(), LHS, RHS); 706 } 707 708 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 709 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), 710 N->getValueType(0))); 711 } 712 713 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 714 SDValue Chain = N->getOperand(0); // Get the chain. 715 SDValue Ptr = N->getOperand(1); // Get the pointer. 716 EVT VT = N->getValueType(0); 717 SDLoc dl(N); 718 719 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); 720 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT); 721 // The argument is passed as NumRegs registers of type RegVT. 722 723 SmallVector<SDValue, 8> Parts(NumRegs); 724 for (unsigned i = 0; i < NumRegs; ++i) { 725 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), 726 N->getConstantOperandVal(3)); 727 Chain = Parts[i].getValue(1); 728 } 729 730 // Handle endianness of the load. 731 if (TLI.isBigEndian()) 732 std::reverse(Parts.begin(), Parts.end()); 733 734 // Assemble the parts in the promoted type. 735 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 736 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 737 for (unsigned i = 1; i < NumRegs; ++i) { 738 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 739 // Shift it to the right position and "or" it in. 740 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 741 DAG.getConstant(i * RegVT.getSizeInBits(), 742 TLI.getPointerTy())); 743 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 744 } 745 746 // Modified the chain result - switch anything that used the old chain to 747 // use the new one. 748 ReplaceValueWith(SDValue(N, 1), Chain); 749 750 return Res; 751 } 752 753 //===----------------------------------------------------------------------===// 754 // Integer Operand Promotion 755 //===----------------------------------------------------------------------===// 756 757 /// PromoteIntegerOperand - This method is called when the specified operand of 758 /// the specified node is found to need promotion. At this point, all of the 759 /// result types of the node are known to be legal, but other operands of the 760 /// node may need promotion or expansion as well as the specified one. 761 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 762 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n"); 763 SDValue Res = SDValue(); 764 765 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 766 return false; 767 768 switch (N->getOpcode()) { 769 default: 770 #ifndef NDEBUG 771 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": "; 772 N->dump(&DAG); dbgs() << "\n"; 773 #endif 774 llvm_unreachable("Do not know how to promote this operator's operand!"); 775 776 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 777 case ISD::ATOMIC_STORE: 778 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N)); 779 break; 780 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break; 781 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 782 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 783 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 784 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 785 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; 786 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; 787 case ISD::CONVERT_RNDSAT: 788 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 789 case ISD::INSERT_VECTOR_ELT: 790 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 791 case ISD::SCALAR_TO_VECTOR: 792 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break; 793 case ISD::VSELECT: 794 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 795 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 796 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 797 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 798 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 799 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 800 OpNo); break; 801 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 802 case ISD::FP16_TO_FP32: 803 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 804 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 805 806 case ISD::SHL: 807 case ISD::SRA: 808 case ISD::SRL: 809 case ISD::ROTL: 810 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 811 } 812 813 // If the result is null, the sub-method took care of registering results etc. 814 if (!Res.getNode()) return false; 815 816 // If the result is N, the sub-method updated N in place. Tell the legalizer 817 // core about this. 818 if (Res.getNode() == N) 819 return true; 820 821 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 822 "Invalid operand expansion"); 823 824 ReplaceValueWith(SDValue(N, 0), Res); 825 return false; 826 } 827 828 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is 829 /// shared among BR_CC, SELECT_CC, and SETCC handlers. 830 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 831 ISD::CondCode CCCode) { 832 // We have to insert explicit sign or zero extends. Note that we could 833 // insert sign extends for ALL conditions, but zero extend is cheaper on 834 // many machines (an AND instead of two shifts), so prefer it. 835 switch (CCCode) { 836 default: llvm_unreachable("Unknown integer comparison!"); 837 case ISD::SETEQ: 838 case ISD::SETNE: 839 case ISD::SETUGE: 840 case ISD::SETUGT: 841 case ISD::SETULE: 842 case ISD::SETULT: 843 // ALL of these operations will work if we either sign or zero extend 844 // the operands (including the unsigned comparisons!). Zero extend is 845 // usually a simpler/cheaper operation, so prefer it. 846 NewLHS = ZExtPromotedInteger(NewLHS); 847 NewRHS = ZExtPromotedInteger(NewRHS); 848 break; 849 case ISD::SETGE: 850 case ISD::SETGT: 851 case ISD::SETLT: 852 case ISD::SETLE: 853 NewLHS = SExtPromotedInteger(NewLHS); 854 NewRHS = SExtPromotedInteger(NewRHS); 855 break; 856 } 857 } 858 859 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 860 SDValue Op = GetPromotedInteger(N->getOperand(0)); 861 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op); 862 } 863 864 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) { 865 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 866 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(), 867 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(), 868 N->getOrdering(), N->getSynchScope()); 869 } 870 871 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) { 872 // This should only occur in unusual situations like bitcasting to an 873 // x86_fp80, so just turn it into a store+load 874 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0)); 875 } 876 877 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 878 assert(OpNo == 2 && "Don't know how to promote this operand!"); 879 880 SDValue LHS = N->getOperand(2); 881 SDValue RHS = N->getOperand(3); 882 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 883 884 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 885 // legal types. 886 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 887 N->getOperand(1), LHS, RHS, N->getOperand(4)), 888 0); 889 } 890 891 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 892 assert(OpNo == 1 && "only know how to promote condition"); 893 894 // Promote all the way up to the canonical SetCC type. 895 EVT SVT = getSetCCResultType(MVT::Other); 896 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 897 898 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 899 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond, 900 N->getOperand(2)), 0); 901 } 902 903 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 904 // Since the result type is legal, the operands must promote to it. 905 EVT OVT = N->getOperand(0).getValueType(); 906 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 907 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 908 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 909 SDLoc dl(N); 910 911 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 912 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 913 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 914 } 915 916 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 917 // The vector type is legal but the element type is not. This implies 918 // that the vector is a power-of-two in length and that the element 919 // type does not have a strange size (eg: it is not i1). 920 EVT VecVT = N->getValueType(0); 921 unsigned NumElts = VecVT.getVectorNumElements(); 922 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 923 924 // Promote the inserted value. The type does not need to match the 925 // vector element type. Check that any extra bits introduced will be 926 // truncated away. 927 assert(N->getOperand(0).getValueType().getSizeInBits() >= 928 N->getValueType(0).getVectorElementType().getSizeInBits() && 929 "Type of inserted value narrower than vector element type!"); 930 931 SmallVector<SDValue, 16> NewOps; 932 for (unsigned i = 0; i < NumElts; ++i) 933 NewOps.push_back(GetPromotedInteger(N->getOperand(i))); 934 935 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0); 936 } 937 938 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 939 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 940 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 941 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 942 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 943 "can only promote integer arguments"); 944 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 945 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp, 946 N->getOperand(1), N->getOperand(2), 947 N->getOperand(3), N->getOperand(4), CvtCode); 948 } 949 950 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 951 unsigned OpNo) { 952 if (OpNo == 1) { 953 // Promote the inserted value. This is valid because the type does not 954 // have to match the vector element type. 955 956 // Check that any extra bits introduced will be truncated away. 957 assert(N->getOperand(1).getValueType().getSizeInBits() >= 958 N->getValueType(0).getVectorElementType().getSizeInBits() && 959 "Type of inserted value narrower than vector element type!"); 960 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 961 GetPromotedInteger(N->getOperand(1)), 962 N->getOperand(2)), 963 0); 964 } 965 966 assert(OpNo == 2 && "Different operand and result vector types?"); 967 968 // Promote the index. 969 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N), 970 TLI.getVectorIdxTy()); 971 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 972 N->getOperand(1), Idx), 0); 973 } 974 975 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) { 976 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote 977 // the operand in place. 978 return SDValue(DAG.UpdateNodeOperands(N, 979 GetPromotedInteger(N->getOperand(0))), 0); 980 } 981 982 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 983 assert(OpNo == 0 && "Only know how to promote the condition!"); 984 SDValue Cond = N->getOperand(0); 985 EVT OpTy = N->getOperand(1).getValueType(); 986 987 // Promote all the way up to the canonical SetCC type. 988 EVT SVT = getSetCCResultType(N->getOpcode() == ISD::SELECT ? 989 OpTy.getScalarType() : OpTy); 990 Cond = PromoteTargetBoolean(Cond, SVT); 991 992 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1), 993 N->getOperand(2)), 0); 994 } 995 996 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 997 assert(OpNo == 0 && "Don't know how to promote this operand!"); 998 999 SDValue LHS = N->getOperand(0); 1000 SDValue RHS = N->getOperand(1); 1001 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 1002 1003 // The CC (#4) and the possible return values (#2 and #3) have legal types. 1004 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2), 1005 N->getOperand(3), N->getOperand(4)), 0); 1006 } 1007 1008 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 1009 assert(OpNo == 0 && "Don't know how to promote this operand!"); 1010 1011 SDValue LHS = N->getOperand(0); 1012 SDValue RHS = N->getOperand(1); 1013 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 1014 1015 // The CC (#2) is always legal. 1016 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0); 1017 } 1018 1019 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { 1020 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 1021 ZExtPromotedInteger(N->getOperand(1))), 0); 1022 } 1023 1024 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 1025 SDValue Op = GetPromotedInteger(N->getOperand(0)); 1026 SDLoc dl(N); 1027 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 1028 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 1029 Op, DAG.getValueType(N->getOperand(0).getValueType())); 1030 } 1031 1032 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 1033 return SDValue(DAG.UpdateNodeOperands(N, 1034 SExtPromotedInteger(N->getOperand(0))), 0); 1035 } 1036 1037 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 1038 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 1039 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 1040 unsigned Alignment = N->getAlignment(); 1041 bool isVolatile = N->isVolatile(); 1042 bool isNonTemporal = N->isNonTemporal(); 1043 SDLoc dl(N); 1044 1045 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 1046 1047 // Truncate the value and store the result. 1048 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(), 1049 N->getMemoryVT(), 1050 isVolatile, isNonTemporal, Alignment); 1051 } 1052 1053 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 1054 SDValue Op = GetPromotedInteger(N->getOperand(0)); 1055 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op); 1056 } 1057 1058 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 1059 return SDValue(DAG.UpdateNodeOperands(N, 1060 ZExtPromotedInteger(N->getOperand(0))), 0); 1061 } 1062 1063 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 1064 SDLoc dl(N); 1065 SDValue Op = GetPromotedInteger(N->getOperand(0)); 1066 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 1067 return DAG.getZeroExtendInReg(Op, dl, 1068 N->getOperand(0).getValueType().getScalarType()); 1069 } 1070 1071 1072 //===----------------------------------------------------------------------===// 1073 // Integer Result Expansion 1074 //===----------------------------------------------------------------------===// 1075 1076 /// ExpandIntegerResult - This method is called when the specified result of the 1077 /// specified node is found to need expansion. At this point, the node may also 1078 /// have invalid operands or may have other results that need promotion, we just 1079 /// know that (at least) one result needs expansion. 1080 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 1081 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n"); 1082 SDValue Lo, Hi; 1083 Lo = Hi = SDValue(); 1084 1085 // See if the target wants to custom expand this node. 1086 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 1087 return; 1088 1089 switch (N->getOpcode()) { 1090 default: 1091 #ifndef NDEBUG 1092 dbgs() << "ExpandIntegerResult #" << ResNo << ": "; 1093 N->dump(&DAG); dbgs() << "\n"; 1094 #endif 1095 llvm_unreachable("Do not know how to expand the result of this operator!"); 1096 1097 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 1098 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 1099 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1100 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 1101 1102 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; 1103 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 1104 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 1105 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 1106 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 1107 1108 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 1109 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 1110 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 1111 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 1112 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 1113 case ISD::CTLZ_ZERO_UNDEF: 1114 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 1115 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 1116 case ISD::CTTZ_ZERO_UNDEF: 1117 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 1118 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 1119 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 1120 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 1121 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 1122 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1123 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1124 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1125 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1126 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1127 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1128 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1129 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1130 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break; 1131 1132 case ISD::ATOMIC_LOAD_ADD: 1133 case ISD::ATOMIC_LOAD_SUB: 1134 case ISD::ATOMIC_LOAD_AND: 1135 case ISD::ATOMIC_LOAD_OR: 1136 case ISD::ATOMIC_LOAD_XOR: 1137 case ISD::ATOMIC_LOAD_NAND: 1138 case ISD::ATOMIC_LOAD_MIN: 1139 case ISD::ATOMIC_LOAD_MAX: 1140 case ISD::ATOMIC_LOAD_UMIN: 1141 case ISD::ATOMIC_LOAD_UMAX: 1142 case ISD::ATOMIC_SWAP: 1143 case ISD::ATOMIC_CMP_SWAP: { 1144 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N); 1145 SplitInteger(Tmp.first, Lo, Hi); 1146 ReplaceValueWith(SDValue(N, 1), Tmp.second); 1147 break; 1148 } 1149 1150 case ISD::AND: 1151 case ISD::OR: 1152 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1153 1154 case ISD::ADD: 1155 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1156 1157 case ISD::ADDC: 1158 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1159 1160 case ISD::ADDE: 1161 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1162 1163 case ISD::SHL: 1164 case ISD::SRA: 1165 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1166 1167 case ISD::SADDO: 1168 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break; 1169 case ISD::UADDO: 1170 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break; 1171 case ISD::UMULO: 1172 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; 1173 } 1174 1175 // If Lo/Hi is null, the sub-method took care of registering results etc. 1176 if (Lo.getNode()) 1177 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1178 } 1179 1180 /// Lower an atomic node to the appropriate builtin call. 1181 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) { 1182 unsigned Opc = Node->getOpcode(); 1183 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 1184 RTLIB::Libcall LC; 1185 1186 switch (Opc) { 1187 default: 1188 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 1189 case ISD::ATOMIC_SWAP: 1190 switch (VT.SimpleTy) { 1191 default: llvm_unreachable("Unexpected value type for atomic!"); 1192 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 1193 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 1194 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 1195 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 1196 } 1197 break; 1198 case ISD::ATOMIC_CMP_SWAP: 1199 switch (VT.SimpleTy) { 1200 default: llvm_unreachable("Unexpected value type for atomic!"); 1201 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 1202 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 1203 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 1204 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 1205 } 1206 break; 1207 case ISD::ATOMIC_LOAD_ADD: 1208 switch (VT.SimpleTy) { 1209 default: llvm_unreachable("Unexpected value type for atomic!"); 1210 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 1211 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 1212 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 1213 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 1214 } 1215 break; 1216 case ISD::ATOMIC_LOAD_SUB: 1217 switch (VT.SimpleTy) { 1218 default: llvm_unreachable("Unexpected value type for atomic!"); 1219 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 1220 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 1221 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 1222 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 1223 } 1224 break; 1225 case ISD::ATOMIC_LOAD_AND: 1226 switch (VT.SimpleTy) { 1227 default: llvm_unreachable("Unexpected value type for atomic!"); 1228 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 1229 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 1230 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 1231 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 1232 } 1233 break; 1234 case ISD::ATOMIC_LOAD_OR: 1235 switch (VT.SimpleTy) { 1236 default: llvm_unreachable("Unexpected value type for atomic!"); 1237 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 1238 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 1239 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 1240 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 1241 } 1242 break; 1243 case ISD::ATOMIC_LOAD_XOR: 1244 switch (VT.SimpleTy) { 1245 default: llvm_unreachable("Unexpected value type for atomic!"); 1246 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 1247 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 1248 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 1249 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 1250 } 1251 break; 1252 case ISD::ATOMIC_LOAD_NAND: 1253 switch (VT.SimpleTy) { 1254 default: llvm_unreachable("Unexpected value type for atomic!"); 1255 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 1256 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 1257 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 1258 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 1259 } 1260 break; 1261 } 1262 1263 return ExpandChainLibCall(LC, Node, false); 1264 } 1265 1266 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1267 /// and the shift amount is a constant 'Amt'. Expand the operation. 1268 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1269 SDValue &Lo, SDValue &Hi) { 1270 SDLoc DL(N); 1271 // Expand the incoming operand to be shifted, so that we have its parts 1272 SDValue InL, InH; 1273 GetExpandedInteger(N->getOperand(0), InL, InH); 1274 1275 EVT NVT = InL.getValueType(); 1276 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1277 unsigned NVTBits = NVT.getSizeInBits(); 1278 EVT ShTy = N->getOperand(1).getValueType(); 1279 1280 if (N->getOpcode() == ISD::SHL) { 1281 if (Amt > VTBits) { 1282 Lo = Hi = DAG.getConstant(0, NVT); 1283 } else if (Amt > NVTBits) { 1284 Lo = DAG.getConstant(0, NVT); 1285 Hi = DAG.getNode(ISD::SHL, DL, 1286 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy)); 1287 } else if (Amt == NVTBits) { 1288 Lo = DAG.getConstant(0, NVT); 1289 Hi = InL; 1290 } else if (Amt == 1 && 1291 TLI.isOperationLegalOrCustom(ISD::ADDC, 1292 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) { 1293 // Emit this X << 1 as X+X. 1294 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1295 SDValue LoOps[2] = { InL, InL }; 1296 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2); 1297 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1298 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3); 1299 } else { 1300 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1301 Hi = DAG.getNode(ISD::OR, DL, NVT, 1302 DAG.getNode(ISD::SHL, DL, NVT, InH, 1303 DAG.getConstant(Amt, ShTy)), 1304 DAG.getNode(ISD::SRL, DL, NVT, InL, 1305 DAG.getConstant(NVTBits-Amt, ShTy))); 1306 } 1307 return; 1308 } 1309 1310 if (N->getOpcode() == ISD::SRL) { 1311 if (Amt > VTBits) { 1312 Lo = DAG.getConstant(0, NVT); 1313 Hi = DAG.getConstant(0, NVT); 1314 } else if (Amt > NVTBits) { 1315 Lo = DAG.getNode(ISD::SRL, DL, 1316 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1317 Hi = DAG.getConstant(0, NVT); 1318 } else if (Amt == NVTBits) { 1319 Lo = InH; 1320 Hi = DAG.getConstant(0, NVT); 1321 } else { 1322 Lo = DAG.getNode(ISD::OR, DL, NVT, 1323 DAG.getNode(ISD::SRL, DL, NVT, InL, 1324 DAG.getConstant(Amt, ShTy)), 1325 DAG.getNode(ISD::SHL, DL, NVT, InH, 1326 DAG.getConstant(NVTBits-Amt, ShTy))); 1327 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1328 } 1329 return; 1330 } 1331 1332 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1333 if (Amt > VTBits) { 1334 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1335 DAG.getConstant(NVTBits-1, ShTy)); 1336 } else if (Amt > NVTBits) { 1337 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1338 DAG.getConstant(Amt-NVTBits, ShTy)); 1339 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1340 DAG.getConstant(NVTBits-1, ShTy)); 1341 } else if (Amt == NVTBits) { 1342 Lo = InH; 1343 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1344 DAG.getConstant(NVTBits-1, ShTy)); 1345 } else { 1346 Lo = DAG.getNode(ISD::OR, DL, NVT, 1347 DAG.getNode(ISD::SRL, DL, NVT, InL, 1348 DAG.getConstant(Amt, ShTy)), 1349 DAG.getNode(ISD::SHL, DL, NVT, InH, 1350 DAG.getConstant(NVTBits-Amt, ShTy))); 1351 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1352 } 1353 } 1354 1355 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1356 /// this shift based on knowledge of the high bit of the shift amount. If we 1357 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1358 /// shift amount. 1359 bool DAGTypeLegalizer:: 1360 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1361 SDValue Amt = N->getOperand(1); 1362 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1363 EVT ShTy = Amt.getValueType(); 1364 unsigned ShBits = ShTy.getScalarType().getSizeInBits(); 1365 unsigned NVTBits = NVT.getScalarType().getSizeInBits(); 1366 assert(isPowerOf2_32(NVTBits) && 1367 "Expanded integer type size not a power of two!"); 1368 SDLoc dl(N); 1369 1370 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1371 APInt KnownZero, KnownOne; 1372 DAG.ComputeMaskedBits(N->getOperand(1), KnownZero, KnownOne); 1373 1374 // If we don't know anything about the high bits, exit. 1375 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1376 return false; 1377 1378 // Get the incoming operand to be shifted. 1379 SDValue InL, InH; 1380 GetExpandedInteger(N->getOperand(0), InL, InH); 1381 1382 // If we know that any of the high bits of the shift amount are one, then we 1383 // can do this as a couple of simple shifts. 1384 if (KnownOne.intersects(HighBitMask)) { 1385 // Mask out the high bit, which we know is set. 1386 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1387 DAG.getConstant(~HighBitMask, ShTy)); 1388 1389 switch (N->getOpcode()) { 1390 default: llvm_unreachable("Unknown shift"); 1391 case ISD::SHL: 1392 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1393 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1394 return true; 1395 case ISD::SRL: 1396 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1397 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1398 return true; 1399 case ISD::SRA: 1400 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1401 DAG.getConstant(NVTBits-1, ShTy)); 1402 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1403 return true; 1404 } 1405 } 1406 1407 // If we know that all of the high bits of the shift amount are zero, then we 1408 // can do this as a couple of simple shifts. 1409 if ((KnownZero & HighBitMask) == HighBitMask) { 1410 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined 1411 // shift if x is zero. We can use XOR here because x is known to be smaller 1412 // than 32. 1413 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt, 1414 DAG.getConstant(NVTBits-1, ShTy)); 1415 1416 unsigned Op1, Op2; 1417 switch (N->getOpcode()) { 1418 default: llvm_unreachable("Unknown shift"); 1419 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1420 case ISD::SRL: 1421 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1422 } 1423 1424 // When shifting right the arithmetic for Lo and Hi is swapped. 1425 if (N->getOpcode() != ISD::SHL) 1426 std::swap(InL, InH); 1427 1428 // Use a little trick to get the bits that move from Lo to Hi. First 1429 // shift by one bit. 1430 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy)); 1431 // Then compute the remaining shift with amount-1. 1432 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2); 1433 1434 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt); 1435 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2); 1436 1437 if (N->getOpcode() != ISD::SHL) 1438 std::swap(Hi, Lo); 1439 return true; 1440 } 1441 1442 return false; 1443 } 1444 1445 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift 1446 /// of any size. 1447 bool DAGTypeLegalizer:: 1448 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1449 SDValue Amt = N->getOperand(1); 1450 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1451 EVT ShTy = Amt.getValueType(); 1452 unsigned NVTBits = NVT.getSizeInBits(); 1453 assert(isPowerOf2_32(NVTBits) && 1454 "Expanded integer type size not a power of two!"); 1455 SDLoc dl(N); 1456 1457 // Get the incoming operand to be shifted. 1458 SDValue InL, InH; 1459 GetExpandedInteger(N->getOperand(0), InL, InH); 1460 1461 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); 1462 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); 1463 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1464 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy), 1465 Amt, NVBitsNode, ISD::SETULT); 1466 1467 SDValue LoS, HiS, LoL, HiL; 1468 switch (N->getOpcode()) { 1469 default: llvm_unreachable("Unknown shift"); 1470 case ISD::SHL: 1471 // Short: ShAmt < NVTBits 1472 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 1473 HiS = DAG.getNode(ISD::OR, dl, NVT, 1474 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 1475 // FIXME: If Amt is zero, the following shift generates an undefined result 1476 // on some architectures. 1477 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack)); 1478 1479 // Long: ShAmt >= NVTBits 1480 LoL = DAG.getConstant(0, NVT); // Lo part is zero. 1481 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part. 1482 1483 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL); 1484 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL); 1485 return true; 1486 case ISD::SRL: 1487 // Short: ShAmt < NVTBits 1488 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 1489 LoS = DAG.getNode(ISD::OR, dl, NVT, 1490 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1491 // FIXME: If Amt is zero, the following shift generates an undefined result 1492 // on some architectures. 1493 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1494 1495 // Long: ShAmt >= NVTBits 1496 HiL = DAG.getConstant(0, NVT); // Hi part is zero. 1497 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1498 1499 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL); 1500 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL); 1501 return true; 1502 case ISD::SRA: 1503 // Short: ShAmt < NVTBits 1504 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 1505 LoS = DAG.getNode(ISD::OR, dl, NVT, 1506 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1507 // FIXME: If Amt is zero, the following shift generates an undefined result 1508 // on some architectures. 1509 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1510 1511 // Long: ShAmt >= NVTBits 1512 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part. 1513 DAG.getConstant(NVTBits-1, ShTy)); 1514 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1515 1516 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL); 1517 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL); 1518 return true; 1519 } 1520 } 1521 1522 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1523 SDValue &Lo, SDValue &Hi) { 1524 SDLoc dl(N); 1525 // Expand the subcomponents. 1526 SDValue LHSL, LHSH, RHSL, RHSH; 1527 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1528 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1529 1530 EVT NVT = LHSL.getValueType(); 1531 SDValue LoOps[2] = { LHSL, RHSL }; 1532 SDValue HiOps[3] = { LHSH, RHSH }; 1533 1534 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1535 // them. TODO: Teach operation legalization how to expand unsupported 1536 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1537 // a carry of type MVT::Glue, but there doesn't seem to be any way to 1538 // generate a value of this type in the expanded code sequence. 1539 bool hasCarry = 1540 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1541 ISD::ADDC : ISD::SUBC, 1542 TLI.getTypeToExpandTo(*DAG.getContext(), NVT)); 1543 1544 if (hasCarry) { 1545 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1546 if (N->getOpcode() == ISD::ADD) { 1547 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1548 HiOps[2] = Lo.getValue(1); 1549 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1550 } else { 1551 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1552 HiOps[2] = Lo.getValue(1); 1553 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1554 } 1555 return; 1556 } 1557 1558 if (N->getOpcode() == ISD::ADD) { 1559 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1560 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1561 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0], 1562 ISD::SETULT); 1563 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1, 1564 DAG.getConstant(1, NVT), 1565 DAG.getConstant(0, NVT)); 1566 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1], 1567 ISD::SETULT); 1568 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2, 1569 DAG.getConstant(1, NVT), Carry1); 1570 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1571 } else { 1572 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1573 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1574 SDValue Cmp = 1575 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()), 1576 LoOps[0], LoOps[1], ISD::SETULT); 1577 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp, 1578 DAG.getConstant(1, NVT), 1579 DAG.getConstant(0, NVT)); 1580 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1581 } 1582 } 1583 1584 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1585 SDValue &Lo, SDValue &Hi) { 1586 // Expand the subcomponents. 1587 SDValue LHSL, LHSH, RHSL, RHSH; 1588 SDLoc dl(N); 1589 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1590 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1591 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1592 SDValue LoOps[2] = { LHSL, RHSL }; 1593 SDValue HiOps[3] = { LHSH, RHSH }; 1594 1595 if (N->getOpcode() == ISD::ADDC) { 1596 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1597 HiOps[2] = Lo.getValue(1); 1598 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1599 } else { 1600 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1601 HiOps[2] = Lo.getValue(1); 1602 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1603 } 1604 1605 // Legalized the flag result - switch anything that used the old flag to 1606 // use the new one. 1607 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1608 } 1609 1610 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1611 SDValue &Lo, SDValue &Hi) { 1612 // Expand the subcomponents. 1613 SDValue LHSL, LHSH, RHSL, RHSH; 1614 SDLoc dl(N); 1615 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1616 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1617 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1618 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1619 SDValue HiOps[3] = { LHSH, RHSH }; 1620 1621 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1622 HiOps[2] = Lo.getValue(1); 1623 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1624 1625 // Legalized the flag result - switch anything that used the old flag to 1626 // use the new one. 1627 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1628 } 1629 1630 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo, 1631 SDValue &Lo, SDValue &Hi) { 1632 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo); 1633 SplitInteger(Res, Lo, Hi); 1634 } 1635 1636 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1637 SDValue &Lo, SDValue &Hi) { 1638 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1639 SDLoc dl(N); 1640 SDValue Op = N->getOperand(0); 1641 if (Op.getValueType().bitsLE(NVT)) { 1642 // The low part is any extension of the input (which degenerates to a copy). 1643 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1644 Hi = DAG.getUNDEF(NVT); // The high part is undefined. 1645 } else { 1646 // For example, extension of an i48 to an i64. The operand type necessarily 1647 // promotes to the result type, so will end up being expanded too. 1648 assert(getTypeAction(Op.getValueType()) == 1649 TargetLowering::TypePromoteInteger && 1650 "Only know how to promote this result!"); 1651 SDValue Res = GetPromotedInteger(Op); 1652 assert(Res.getValueType() == N->getValueType(0) && 1653 "Operand over promoted?"); 1654 // Split the promoted operand. This will simplify when it is expanded. 1655 SplitInteger(Res, Lo, Hi); 1656 } 1657 } 1658 1659 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1660 SDValue &Lo, SDValue &Hi) { 1661 SDLoc dl(N); 1662 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1663 EVT NVT = Lo.getValueType(); 1664 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1665 unsigned NVTBits = NVT.getSizeInBits(); 1666 unsigned EVTBits = EVT.getSizeInBits(); 1667 1668 if (NVTBits < EVTBits) { 1669 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1670 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1671 EVTBits - NVTBits))); 1672 } else { 1673 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1674 // The high part replicates the sign bit of Lo, make it explicit. 1675 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1676 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1677 } 1678 } 1679 1680 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1681 SDValue &Lo, SDValue &Hi) { 1682 SDLoc dl(N); 1683 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1684 EVT NVT = Lo.getValueType(); 1685 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1686 unsigned NVTBits = NVT.getSizeInBits(); 1687 unsigned EVTBits = EVT.getSizeInBits(); 1688 1689 if (NVTBits < EVTBits) { 1690 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1691 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1692 EVTBits - NVTBits))); 1693 } else { 1694 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1695 // The high part must be zero, make it explicit. 1696 Hi = DAG.getConstant(0, NVT); 1697 } 1698 } 1699 1700 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1701 SDValue &Lo, SDValue &Hi) { 1702 SDLoc dl(N); 1703 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1704 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1705 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1706 } 1707 1708 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1709 SDValue &Lo, SDValue &Hi) { 1710 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1711 unsigned NBitWidth = NVT.getSizeInBits(); 1712 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1713 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT); 1714 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1715 } 1716 1717 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1718 SDValue &Lo, SDValue &Hi) { 1719 SDLoc dl(N); 1720 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1721 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1722 EVT NVT = Lo.getValueType(); 1723 1724 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi, 1725 DAG.getConstant(0, NVT), ISD::SETNE); 1726 1727 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo); 1728 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi); 1729 1730 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ, 1731 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1732 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1733 Hi = DAG.getConstant(0, NVT); 1734 } 1735 1736 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1737 SDValue &Lo, SDValue &Hi) { 1738 SDLoc dl(N); 1739 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1740 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1741 EVT NVT = Lo.getValueType(); 1742 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 1743 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1744 Hi = DAG.getConstant(0, NVT); 1745 } 1746 1747 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1748 SDValue &Lo, SDValue &Hi) { 1749 SDLoc dl(N); 1750 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1751 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1752 EVT NVT = Lo.getValueType(); 1753 1754 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, 1755 DAG.getConstant(0, NVT), ISD::SETNE); 1756 1757 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo); 1758 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi); 1759 1760 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ, 1761 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1762 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1763 Hi = DAG.getConstant(0, NVT); 1764 } 1765 1766 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1767 SDValue &Hi) { 1768 SDLoc dl(N); 1769 EVT VT = N->getValueType(0); 1770 SDValue Op = N->getOperand(0); 1771 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1772 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1773 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/, dl), 1774 Lo, Hi); 1775 } 1776 1777 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1778 SDValue &Hi) { 1779 SDLoc dl(N); 1780 EVT VT = N->getValueType(0); 1781 SDValue Op = N->getOperand(0); 1782 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1783 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1784 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/, dl), 1785 Lo, Hi); 1786 } 1787 1788 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1789 SDValue &Lo, SDValue &Hi) { 1790 if (ISD::isNormalLoad(N)) { 1791 ExpandRes_NormalLoad(N, Lo, Hi); 1792 return; 1793 } 1794 1795 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1796 1797 EVT VT = N->getValueType(0); 1798 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1799 SDValue Ch = N->getChain(); 1800 SDValue Ptr = N->getBasePtr(); 1801 ISD::LoadExtType ExtType = N->getExtensionType(); 1802 unsigned Alignment = N->getAlignment(); 1803 bool isVolatile = N->isVolatile(); 1804 bool isNonTemporal = N->isNonTemporal(); 1805 bool isInvariant = N->isInvariant(); 1806 SDLoc dl(N); 1807 1808 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1809 1810 if (N->getMemoryVT().bitsLE(NVT)) { 1811 EVT MemVT = N->getMemoryVT(); 1812 1813 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1814 MemVT, isVolatile, isNonTemporal, Alignment); 1815 1816 // Remember the chain. 1817 Ch = Lo.getValue(1); 1818 1819 if (ExtType == ISD::SEXTLOAD) { 1820 // The high part is obtained by SRA'ing all but one of the bits of the 1821 // lo part. 1822 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1823 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1824 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1825 } else if (ExtType == ISD::ZEXTLOAD) { 1826 // The high part is just a zero. 1827 Hi = DAG.getConstant(0, NVT); 1828 } else { 1829 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1830 // The high part is undefined. 1831 Hi = DAG.getUNDEF(NVT); 1832 } 1833 } else if (TLI.isLittleEndian()) { 1834 // Little-endian - low bits are at low addresses. 1835 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), 1836 isVolatile, isNonTemporal, isInvariant, Alignment); 1837 1838 unsigned ExcessBits = 1839 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1840 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 1841 1842 // Increment the pointer to the other half. 1843 unsigned IncrementSize = NVT.getSizeInBits()/8; 1844 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1845 DAG.getIntPtrConstant(IncrementSize)); 1846 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, 1847 N->getPointerInfo().getWithOffset(IncrementSize), NEVT, 1848 isVolatile, isNonTemporal, 1849 MinAlign(Alignment, IncrementSize)); 1850 1851 // Build a factor node to remember that this load is independent of the 1852 // other one. 1853 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1854 Hi.getValue(1)); 1855 } else { 1856 // Big-endian - high bits are at low addresses. Favor aligned loads at 1857 // the cost of some bit-fiddling. 1858 EVT MemVT = N->getMemoryVT(); 1859 unsigned EBytes = MemVT.getStoreSize(); 1860 unsigned IncrementSize = NVT.getSizeInBits()/8; 1861 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1862 1863 // Load both the high bits and maybe some of the low bits. 1864 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1865 EVT::getIntegerVT(*DAG.getContext(), 1866 MemVT.getSizeInBits() - ExcessBits), 1867 isVolatile, isNonTemporal, Alignment); 1868 1869 // Increment the pointer to the other half. 1870 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1871 DAG.getIntPtrConstant(IncrementSize)); 1872 // Load the rest of the low bits. 1873 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, 1874 N->getPointerInfo().getWithOffset(IncrementSize), 1875 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 1876 isVolatile, isNonTemporal, 1877 MinAlign(Alignment, IncrementSize)); 1878 1879 // Build a factor node to remember that this load is independent of the 1880 // other one. 1881 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1882 Hi.getValue(1)); 1883 1884 if (ExcessBits < NVT.getSizeInBits()) { 1885 // Transfer low bits from the bottom of Hi to the top of Lo. 1886 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1887 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1888 DAG.getConstant(ExcessBits, 1889 TLI.getPointerTy()))); 1890 // Move high bits to the right position in Hi. 1891 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1892 NVT, Hi, 1893 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1894 TLI.getPointerTy())); 1895 } 1896 } 1897 1898 // Legalized the chain result - switch anything that used the old chain to 1899 // use the new one. 1900 ReplaceValueWith(SDValue(N, 1), Ch); 1901 } 1902 1903 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1904 SDValue &Lo, SDValue &Hi) { 1905 SDLoc dl(N); 1906 SDValue LL, LH, RL, RH; 1907 GetExpandedInteger(N->getOperand(0), LL, LH); 1908 GetExpandedInteger(N->getOperand(1), RL, RH); 1909 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1910 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1911 } 1912 1913 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1914 SDValue &Lo, SDValue &Hi) { 1915 EVT VT = N->getValueType(0); 1916 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1917 SDLoc dl(N); 1918 1919 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1920 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1921 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1922 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1923 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1924 SDValue LL, LH, RL, RH; 1925 GetExpandedInteger(N->getOperand(0), LL, LH); 1926 GetExpandedInteger(N->getOperand(1), RL, RH); 1927 unsigned OuterBitSize = VT.getSizeInBits(); 1928 unsigned InnerBitSize = NVT.getSizeInBits(); 1929 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1930 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1931 1932 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1933 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1934 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1935 // The inputs are both zero-extended. 1936 if (HasUMUL_LOHI) { 1937 // We can emit a umul_lohi. 1938 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1939 Hi = SDValue(Lo.getNode(), 1); 1940 return; 1941 } 1942 if (HasMULHU) { 1943 // We can emit a mulhu+mul. 1944 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1945 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1946 return; 1947 } 1948 } 1949 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1950 // The input values are both sign-extended. 1951 if (HasSMUL_LOHI) { 1952 // We can emit a smul_lohi. 1953 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1954 Hi = SDValue(Lo.getNode(), 1); 1955 return; 1956 } 1957 if (HasMULHS) { 1958 // We can emit a mulhs+mul. 1959 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1960 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1961 return; 1962 } 1963 } 1964 if (HasUMUL_LOHI) { 1965 // Lo,Hi = umul LHS, RHS. 1966 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1967 DAG.getVTList(NVT, NVT), LL, RL); 1968 Lo = UMulLOHI; 1969 Hi = UMulLOHI.getValue(1); 1970 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1971 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1972 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1973 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1974 return; 1975 } 1976 if (HasMULHU) { 1977 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1978 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1979 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1980 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1981 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1982 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1983 return; 1984 } 1985 } 1986 1987 // If nothing else, we can make a libcall. 1988 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1989 if (VT == MVT::i16) 1990 LC = RTLIB::MUL_I16; 1991 else if (VT == MVT::i32) 1992 LC = RTLIB::MUL_I32; 1993 else if (VT == MVT::i64) 1994 LC = RTLIB::MUL_I64; 1995 else if (VT == MVT::i128) 1996 LC = RTLIB::MUL_I128; 1997 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1998 1999 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2000 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/, dl), 2001 Lo, Hi); 2002 } 2003 2004 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node, 2005 SDValue &Lo, SDValue &Hi) { 2006 SDValue LHS = Node->getOperand(0); 2007 SDValue RHS = Node->getOperand(1); 2008 SDLoc dl(Node); 2009 2010 // Expand the result by simply replacing it with the equivalent 2011 // non-overflow-checking operation. 2012 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2013 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2014 LHS, RHS); 2015 SplitInteger(Sum, Lo, Hi); 2016 2017 // Compute the overflow. 2018 // 2019 // LHSSign -> LHS >= 0 2020 // RHSSign -> RHS >= 0 2021 // SumSign -> Sum >= 0 2022 // 2023 // Add: 2024 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2025 // Sub: 2026 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2027 // 2028 EVT OType = Node->getValueType(1); 2029 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2030 2031 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2032 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2033 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2034 Node->getOpcode() == ISD::SADDO ? 2035 ISD::SETEQ : ISD::SETNE); 2036 2037 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2038 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2039 2040 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2041 2042 // Use the calculated overflow everywhere. 2043 ReplaceValueWith(SDValue(Node, 1), Cmp); 2044 } 2045 2046 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 2047 SDValue &Lo, SDValue &Hi) { 2048 EVT VT = N->getValueType(0); 2049 SDLoc dl(N); 2050 2051 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2052 if (VT == MVT::i16) 2053 LC = RTLIB::SDIV_I16; 2054 else if (VT == MVT::i32) 2055 LC = RTLIB::SDIV_I32; 2056 else if (VT == MVT::i64) 2057 LC = RTLIB::SDIV_I64; 2058 else if (VT == MVT::i128) 2059 LC = RTLIB::SDIV_I128; 2060 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 2061 2062 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2063 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl), Lo, Hi); 2064 } 2065 2066 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 2067 SDValue &Lo, SDValue &Hi) { 2068 EVT VT = N->getValueType(0); 2069 SDLoc dl(N); 2070 2071 // If we can emit an efficient shift operation, do so now. Check to see if 2072 // the RHS is a constant. 2073 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2074 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 2075 2076 // If we can determine that the high bit of the shift is zero or one, even if 2077 // the low bits are variable, emit this shift in an optimized form. 2078 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 2079 return; 2080 2081 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 2082 unsigned PartsOpc; 2083 if (N->getOpcode() == ISD::SHL) { 2084 PartsOpc = ISD::SHL_PARTS; 2085 } else if (N->getOpcode() == ISD::SRL) { 2086 PartsOpc = ISD::SRL_PARTS; 2087 } else { 2088 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 2089 PartsOpc = ISD::SRA_PARTS; 2090 } 2091 2092 // Next check to see if the target supports this SHL_PARTS operation or if it 2093 // will custom expand it. 2094 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2095 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 2096 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 2097 Action == TargetLowering::Custom) { 2098 // Expand the subcomponents. 2099 SDValue LHSL, LHSH; 2100 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 2101 EVT VT = LHSL.getValueType(); 2102 2103 // If the shift amount operand is coming from a vector legalization it may 2104 // have an illegal type. Fix that first by casting the operand, otherwise 2105 // the new SHL_PARTS operation would need further legalization. 2106 SDValue ShiftOp = N->getOperand(1); 2107 EVT ShiftTy = TLI.getShiftAmountTy(VT); 2108 assert(ShiftTy.getScalarType().getSizeInBits() >= 2109 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) && 2110 "ShiftAmountTy is too small to cover the range of this type!"); 2111 if (ShiftOp.getValueType() != ShiftTy) 2112 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); 2113 2114 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; 2115 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); 2116 Hi = Lo.getValue(1); 2117 return; 2118 } 2119 2120 // Otherwise, emit a libcall. 2121 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2122 bool isSigned; 2123 if (N->getOpcode() == ISD::SHL) { 2124 isSigned = false; /*sign irrelevant*/ 2125 if (VT == MVT::i16) 2126 LC = RTLIB::SHL_I16; 2127 else if (VT == MVT::i32) 2128 LC = RTLIB::SHL_I32; 2129 else if (VT == MVT::i64) 2130 LC = RTLIB::SHL_I64; 2131 else if (VT == MVT::i128) 2132 LC = RTLIB::SHL_I128; 2133 } else if (N->getOpcode() == ISD::SRL) { 2134 isSigned = false; 2135 if (VT == MVT::i16) 2136 LC = RTLIB::SRL_I16; 2137 else if (VT == MVT::i32) 2138 LC = RTLIB::SRL_I32; 2139 else if (VT == MVT::i64) 2140 LC = RTLIB::SRL_I64; 2141 else if (VT == MVT::i128) 2142 LC = RTLIB::SRL_I128; 2143 } else { 2144 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 2145 isSigned = true; 2146 if (VT == MVT::i16) 2147 LC = RTLIB::SRA_I16; 2148 else if (VT == MVT::i32) 2149 LC = RTLIB::SRA_I32; 2150 else if (VT == MVT::i64) 2151 LC = RTLIB::SRA_I64; 2152 else if (VT == MVT::i128) 2153 LC = RTLIB::SRA_I128; 2154 } 2155 2156 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) { 2157 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2158 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 2159 return; 2160 } 2161 2162 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) 2163 llvm_unreachable("Unsupported shift!"); 2164 } 2165 2166 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 2167 SDValue &Lo, SDValue &Hi) { 2168 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2169 SDLoc dl(N); 2170 SDValue Op = N->getOperand(0); 2171 if (Op.getValueType().bitsLE(NVT)) { 2172 // The low part is sign extension of the input (degenerates to a copy). 2173 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 2174 // The high part is obtained by SRA'ing all but one of the bits of low part. 2175 unsigned LoSize = NVT.getSizeInBits(); 2176 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 2177 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 2178 } else { 2179 // For example, extension of an i48 to an i64. The operand type necessarily 2180 // promotes to the result type, so will end up being expanded too. 2181 assert(getTypeAction(Op.getValueType()) == 2182 TargetLowering::TypePromoteInteger && 2183 "Only know how to promote this result!"); 2184 SDValue Res = GetPromotedInteger(Op); 2185 assert(Res.getValueType() == N->getValueType(0) && 2186 "Operand over promoted?"); 2187 // Split the promoted operand. This will simplify when it is expanded. 2188 SplitInteger(Res, Lo, Hi); 2189 unsigned ExcessBits = 2190 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2191 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 2192 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 2193 ExcessBits))); 2194 } 2195 } 2196 2197 void DAGTypeLegalizer:: 2198 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 2199 SDLoc dl(N); 2200 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2201 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2202 2203 if (EVT.bitsLE(Lo.getValueType())) { 2204 // sext_inreg the low part if needed. 2205 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 2206 N->getOperand(1)); 2207 2208 // The high part gets the sign extension from the lo-part. This handles 2209 // things like sextinreg V:i64 from i8. 2210 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 2211 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 2212 TLI.getPointerTy())); 2213 } else { 2214 // For example, extension of an i48 to an i64. Leave the low part alone, 2215 // sext_inreg the high part. 2216 unsigned ExcessBits = 2217 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 2218 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 2219 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 2220 ExcessBits))); 2221 } 2222 } 2223 2224 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 2225 SDValue &Lo, SDValue &Hi) { 2226 EVT VT = N->getValueType(0); 2227 SDLoc dl(N); 2228 2229 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2230 if (VT == MVT::i16) 2231 LC = RTLIB::SREM_I16; 2232 else if (VT == MVT::i32) 2233 LC = RTLIB::SREM_I32; 2234 else if (VT == MVT::i64) 2235 LC = RTLIB::SREM_I64; 2236 else if (VT == MVT::i128) 2237 LC = RTLIB::SREM_I128; 2238 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 2239 2240 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2241 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl), Lo, Hi); 2242 } 2243 2244 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 2245 SDValue &Lo, SDValue &Hi) { 2246 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2247 SDLoc dl(N); 2248 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 2249 Hi = DAG.getNode(ISD::SRL, dl, 2250 N->getOperand(0).getValueType(), N->getOperand(0), 2251 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 2252 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 2253 } 2254 2255 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N, 2256 SDValue &Lo, SDValue &Hi) { 2257 SDValue LHS = N->getOperand(0); 2258 SDValue RHS = N->getOperand(1); 2259 SDLoc dl(N); 2260 2261 // Expand the result by simply replacing it with the equivalent 2262 // non-overflow-checking operation. 2263 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ? 2264 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2265 LHS, RHS); 2266 SplitInteger(Sum, Lo, Hi); 2267 2268 // Calculate the overflow: addition overflows iff a + b < a, and subtraction 2269 // overflows iff a - b > a. 2270 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, 2271 N->getOpcode () == ISD::UADDO ? 2272 ISD::SETULT : ISD::SETUGT); 2273 2274 // Use the calculated overflow everywhere. 2275 ReplaceValueWith(SDValue(N, 1), Ofl); 2276 } 2277 2278 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N, 2279 SDValue &Lo, SDValue &Hi) { 2280 EVT VT = N->getValueType(0); 2281 SDLoc dl(N); 2282 2283 // A divide for UMULO should be faster than a function call. 2284 if (N->getOpcode() == ISD::UMULO) { 2285 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1); 2286 2287 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS); 2288 SplitInteger(MUL, Lo, Hi); 2289 2290 // A divide for UMULO will be faster than a function call. Select to 2291 // make sure we aren't using 0. 2292 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT), 2293 RHS, DAG.getConstant(0, VT), ISD::SETEQ); 2294 SDValue NotZero = DAG.getSelect(dl, VT, isZero, 2295 DAG.getConstant(1, VT), RHS); 2296 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero); 2297 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS, 2298 ISD::SETNE); 2299 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero, 2300 DAG.getConstant(0, N->getValueType(1)), 2301 Overflow); 2302 ReplaceValueWith(SDValue(N, 1), Overflow); 2303 return; 2304 } 2305 2306 Type *RetTy = VT.getTypeForEVT(*DAG.getContext()); 2307 EVT PtrVT = TLI.getPointerTy(); 2308 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext()); 2309 2310 // Replace this with a libcall that will check overflow. 2311 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2312 if (VT == MVT::i32) 2313 LC = RTLIB::MULO_I32; 2314 else if (VT == MVT::i64) 2315 LC = RTLIB::MULO_I64; 2316 else if (VT == MVT::i128) 2317 LC = RTLIB::MULO_I128; 2318 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!"); 2319 2320 SDValue Temp = DAG.CreateStackTemporary(PtrVT); 2321 // Temporary for the overflow value, default it to zero. 2322 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, 2323 DAG.getConstant(0, PtrVT), Temp, 2324 MachinePointerInfo(), false, false, 0); 2325 2326 TargetLowering::ArgListTy Args; 2327 TargetLowering::ArgListEntry Entry; 2328 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 2329 EVT ArgVT = N->getOperand(i).getValueType(); 2330 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2331 Entry.Node = N->getOperand(i); 2332 Entry.Ty = ArgTy; 2333 Entry.isSExt = true; 2334 Entry.isZExt = false; 2335 Args.push_back(Entry); 2336 } 2337 2338 // Also pass the address of the overflow check. 2339 Entry.Node = Temp; 2340 Entry.Ty = PtrTy->getPointerTo(); 2341 Entry.isSExt = true; 2342 Entry.isZExt = false; 2343 Args.push_back(Entry); 2344 2345 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT); 2346 TargetLowering:: 2347 CallLoweringInfo CLI(Chain, RetTy, true, false, false, false, 2348 0, TLI.getLibcallCallingConv(LC), 2349 /*isTailCall=*/false, 2350 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2351 Func, Args, DAG, dl); 2352 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); 2353 2354 SplitInteger(CallInfo.first, Lo, Hi); 2355 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, 2356 MachinePointerInfo(), false, false, false, 0); 2357 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2, 2358 DAG.getConstant(0, PtrVT), 2359 ISD::SETNE); 2360 // Use the overflow from the libcall everywhere. 2361 ReplaceValueWith(SDValue(N, 1), Ofl); 2362 } 2363 2364 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 2365 SDValue &Lo, SDValue &Hi) { 2366 EVT VT = N->getValueType(0); 2367 SDLoc dl(N); 2368 2369 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2370 if (VT == MVT::i16) 2371 LC = RTLIB::UDIV_I16; 2372 else if (VT == MVT::i32) 2373 LC = RTLIB::UDIV_I32; 2374 else if (VT == MVT::i64) 2375 LC = RTLIB::UDIV_I64; 2376 else if (VT == MVT::i128) 2377 LC = RTLIB::UDIV_I128; 2378 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 2379 2380 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2381 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl), Lo, Hi); 2382 } 2383 2384 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 2385 SDValue &Lo, SDValue &Hi) { 2386 EVT VT = N->getValueType(0); 2387 SDLoc dl(N); 2388 2389 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2390 if (VT == MVT::i16) 2391 LC = RTLIB::UREM_I16; 2392 else if (VT == MVT::i32) 2393 LC = RTLIB::UREM_I32; 2394 else if (VT == MVT::i64) 2395 LC = RTLIB::UREM_I64; 2396 else if (VT == MVT::i128) 2397 LC = RTLIB::UREM_I128; 2398 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 2399 2400 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2401 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl), Lo, Hi); 2402 } 2403 2404 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 2405 SDValue &Lo, SDValue &Hi) { 2406 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2407 SDLoc dl(N); 2408 SDValue Op = N->getOperand(0); 2409 if (Op.getValueType().bitsLE(NVT)) { 2410 // The low part is zero extension of the input (degenerates to a copy). 2411 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 2412 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 2413 } else { 2414 // For example, extension of an i48 to an i64. The operand type necessarily 2415 // promotes to the result type, so will end up being expanded too. 2416 assert(getTypeAction(Op.getValueType()) == 2417 TargetLowering::TypePromoteInteger && 2418 "Only know how to promote this result!"); 2419 SDValue Res = GetPromotedInteger(Op); 2420 assert(Res.getValueType() == N->getValueType(0) && 2421 "Operand over promoted?"); 2422 // Split the promoted operand. This will simplify when it is expanded. 2423 SplitInteger(Res, Lo, Hi); 2424 unsigned ExcessBits = 2425 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2426 Hi = DAG.getZeroExtendInReg(Hi, dl, 2427 EVT::getIntegerVT(*DAG.getContext(), 2428 ExcessBits)); 2429 } 2430 } 2431 2432 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N, 2433 SDValue &Lo, SDValue &Hi) { 2434 SDLoc dl(N); 2435 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT(); 2436 SDValue Zero = DAG.getConstant(0, VT); 2437 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 2438 N->getOperand(0), 2439 N->getOperand(1), Zero, Zero, 2440 cast<AtomicSDNode>(N)->getMemOperand(), 2441 cast<AtomicSDNode>(N)->getOrdering(), 2442 cast<AtomicSDNode>(N)->getSynchScope()); 2443 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0)); 2444 ReplaceValueWith(SDValue(N, 1), Swap.getValue(1)); 2445 } 2446 2447 //===----------------------------------------------------------------------===// 2448 // Integer Operand Expansion 2449 //===----------------------------------------------------------------------===// 2450 2451 /// ExpandIntegerOperand - This method is called when the specified operand of 2452 /// the specified node is found to need expansion. At this point, all of the 2453 /// result types of the node are known to be legal, but other operands of the 2454 /// node may need promotion or expansion as well as the specified one. 2455 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 2456 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n"); 2457 SDValue Res = SDValue(); 2458 2459 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 2460 return false; 2461 2462 switch (N->getOpcode()) { 2463 default: 2464 #ifndef NDEBUG 2465 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": "; 2466 N->dump(&DAG); dbgs() << "\n"; 2467 #endif 2468 llvm_unreachable("Do not know how to expand this operator's operand!"); 2469 2470 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; 2471 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 2472 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 2473 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 2474 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 2475 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 2476 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 2477 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 2478 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 2479 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 2480 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 2481 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 2482 2483 case ISD::SHL: 2484 case ISD::SRA: 2485 case ISD::SRL: 2486 case ISD::ROTL: 2487 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; 2488 case ISD::RETURNADDR: 2489 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break; 2490 2491 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break; 2492 } 2493 2494 // If the result is null, the sub-method took care of registering results etc. 2495 if (!Res.getNode()) return false; 2496 2497 // If the result is N, the sub-method updated N in place. Tell the legalizer 2498 // core about this. 2499 if (Res.getNode() == N) 2500 return true; 2501 2502 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2503 "Invalid operand expansion"); 2504 2505 ReplaceValueWith(SDValue(N, 0), Res); 2506 return false; 2507 } 2508 2509 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 2510 /// is shared among BR_CC, SELECT_CC, and SETCC handlers. 2511 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 2512 SDValue &NewRHS, 2513 ISD::CondCode &CCCode, 2514 SDLoc dl) { 2515 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 2516 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 2517 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 2518 2519 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2520 if (RHSLo == RHSHi) { 2521 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 2522 if (RHSCST->isAllOnesValue()) { 2523 // Equality comparison to -1. 2524 NewLHS = DAG.getNode(ISD::AND, dl, 2525 LHSLo.getValueType(), LHSLo, LHSHi); 2526 NewRHS = RHSLo; 2527 return; 2528 } 2529 } 2530 } 2531 2532 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 2533 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 2534 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 2535 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2536 return; 2537 } 2538 2539 // If this is a comparison of the sign bit, just look at the top part. 2540 // X > -1, x < 0 2541 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2542 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2543 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2544 NewLHS = LHSHi; 2545 NewRHS = RHSHi; 2546 return; 2547 } 2548 2549 // FIXME: This generated code sucks. 2550 ISD::CondCode LowCC; 2551 switch (CCCode) { 2552 default: llvm_unreachable("Unknown integer setcc!"); 2553 case ISD::SETLT: 2554 case ISD::SETULT: LowCC = ISD::SETULT; break; 2555 case ISD::SETGT: 2556 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2557 case ISD::SETLE: 2558 case ISD::SETULE: LowCC = ISD::SETULE; break; 2559 case ISD::SETGE: 2560 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2561 } 2562 2563 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2564 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2565 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2566 2567 // NOTE: on targets without efficient SELECT of bools, we can always use 2568 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2569 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true, NULL); 2570 SDValue Tmp1, Tmp2; 2571 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()), 2572 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 2573 if (!Tmp1.getNode()) 2574 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), 2575 LHSLo, RHSLo, LowCC); 2576 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()), 2577 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 2578 if (!Tmp2.getNode()) 2579 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2580 getSetCCResultType(LHSHi.getValueType()), 2581 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2582 2583 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2584 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2585 if ((Tmp1C && Tmp1C->isNullValue()) || 2586 (Tmp2C && Tmp2C->isNullValue() && 2587 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2588 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2589 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2590 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2591 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2592 // low part is known false, returns high part. 2593 // For LE / GE, if high part is known false, ignore the low part. 2594 // For LT / GT, if high part is known true, ignore the low part. 2595 NewLHS = Tmp2; 2596 NewRHS = SDValue(); 2597 return; 2598 } 2599 2600 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()), 2601 LHSHi, RHSHi, ISD::SETEQ, false, 2602 DagCombineInfo, dl); 2603 if (!NewLHS.getNode()) 2604 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), 2605 LHSHi, RHSHi, ISD::SETEQ); 2606 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(), 2607 NewLHS, Tmp1, Tmp2); 2608 NewRHS = SDValue(); 2609 } 2610 2611 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2612 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2613 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2614 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N)); 2615 2616 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2617 // against zero to select between true and false values. 2618 if (NewRHS.getNode() == 0) { 2619 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2620 CCCode = ISD::SETNE; 2621 } 2622 2623 // Update N to have the operands specified. 2624 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 2625 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2626 N->getOperand(4)), 0); 2627 } 2628 2629 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2630 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2631 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2632 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N)); 2633 2634 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2635 // against zero to select between true and false values. 2636 if (NewRHS.getNode() == 0) { 2637 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2638 CCCode = ISD::SETNE; 2639 } 2640 2641 // Update N to have the operands specified. 2642 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2643 N->getOperand(2), N->getOperand(3), 2644 DAG.getCondCode(CCCode)), 0); 2645 } 2646 2647 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2648 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2649 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2650 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N)); 2651 2652 // If ExpandSetCCOperands returned a scalar, use it. 2653 if (NewRHS.getNode() == 0) { 2654 assert(NewLHS.getValueType() == N->getValueType(0) && 2655 "Unexpected setcc expansion!"); 2656 return NewLHS; 2657 } 2658 2659 // Otherwise, update N to have the operands specified. 2660 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2661 DAG.getCondCode(CCCode)), 0); 2662 } 2663 2664 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { 2665 // The value being shifted is legal, but the shift amount is too big. 2666 // It follows that either the result of the shift is undefined, or the 2667 // upper half of the shift amount is zero. Just use the lower half. 2668 SDValue Lo, Hi; 2669 GetExpandedInteger(N->getOperand(1), Lo, Hi); 2670 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0); 2671 } 2672 2673 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) { 2674 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This 2675 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this 2676 // constant to valid type. 2677 SDValue Lo, Hi; 2678 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2679 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0); 2680 } 2681 2682 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2683 SDValue Op = N->getOperand(0); 2684 EVT DstVT = N->getValueType(0); 2685 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2686 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2687 "Don't know how to expand this SINT_TO_FP!"); 2688 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)); 2689 } 2690 2691 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2692 if (ISD::isNormalStore(N)) 2693 return ExpandOp_NormalStore(N, OpNo); 2694 2695 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2696 assert(OpNo == 1 && "Can only expand the stored value so far"); 2697 2698 EVT VT = N->getOperand(1).getValueType(); 2699 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2700 SDValue Ch = N->getChain(); 2701 SDValue Ptr = N->getBasePtr(); 2702 unsigned Alignment = N->getAlignment(); 2703 bool isVolatile = N->isVolatile(); 2704 bool isNonTemporal = N->isNonTemporal(); 2705 SDLoc dl(N); 2706 SDValue Lo, Hi; 2707 2708 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2709 2710 if (N->getMemoryVT().bitsLE(NVT)) { 2711 GetExpandedInteger(N->getValue(), Lo, Hi); 2712 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2713 N->getMemoryVT(), isVolatile, isNonTemporal, 2714 Alignment); 2715 } 2716 2717 if (TLI.isLittleEndian()) { 2718 // Little-endian - low bits are at low addresses. 2719 GetExpandedInteger(N->getValue(), Lo, Hi); 2720 2721 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2722 isVolatile, isNonTemporal, Alignment); 2723 2724 unsigned ExcessBits = 2725 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2726 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 2727 2728 // Increment the pointer to the other half. 2729 unsigned IncrementSize = NVT.getSizeInBits()/8; 2730 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2731 DAG.getIntPtrConstant(IncrementSize)); 2732 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, 2733 N->getPointerInfo().getWithOffset(IncrementSize), 2734 NEVT, isVolatile, isNonTemporal, 2735 MinAlign(Alignment, IncrementSize)); 2736 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2737 } 2738 2739 // Big-endian - high bits are at low addresses. Favor aligned stores at 2740 // the cost of some bit-fiddling. 2741 GetExpandedInteger(N->getValue(), Lo, Hi); 2742 2743 EVT ExtVT = N->getMemoryVT(); 2744 unsigned EBytes = ExtVT.getStoreSize(); 2745 unsigned IncrementSize = NVT.getSizeInBits()/8; 2746 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2747 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), 2748 ExtVT.getSizeInBits() - ExcessBits); 2749 2750 if (ExcessBits < NVT.getSizeInBits()) { 2751 // Transfer high bits from the top of Lo to the bottom of Hi. 2752 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2753 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2754 TLI.getPointerTy())); 2755 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2756 DAG.getNode(ISD::SRL, dl, NVT, Lo, 2757 DAG.getConstant(ExcessBits, 2758 TLI.getPointerTy()))); 2759 } 2760 2761 // Store both the high bits and maybe some of the low bits. 2762 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), 2763 HiVT, isVolatile, isNonTemporal, Alignment); 2764 2765 // Increment the pointer to the other half. 2766 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2767 DAG.getIntPtrConstant(IncrementSize)); 2768 // Store the lowest ExcessBits bits in the second half. 2769 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, 2770 N->getPointerInfo().getWithOffset(IncrementSize), 2771 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 2772 isVolatile, isNonTemporal, 2773 MinAlign(Alignment, IncrementSize)); 2774 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2775 } 2776 2777 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2778 SDValue InL, InH; 2779 GetExpandedInteger(N->getOperand(0), InL, InH); 2780 // Just truncate the low part of the source. 2781 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL); 2782 } 2783 2784 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2785 SDValue Op = N->getOperand(0); 2786 EVT SrcVT = Op.getValueType(); 2787 EVT DstVT = N->getValueType(0); 2788 SDLoc dl(N); 2789 2790 // The following optimization is valid only if every value in SrcVT (when 2791 // treated as signed) is representable in DstVT. Check that the mantissa 2792 // size of DstVT is >= than the number of bits in SrcVT -1. 2793 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT); 2794 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 && 2795 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2796 // Do a signed conversion then adjust the result. 2797 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2798 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2799 2800 // The result of the signed conversion needs adjusting if the 'sign bit' of 2801 // the incoming integer was set. To handle this, we dynamically test to see 2802 // if it is set, and, if so, add a fudge factor. 2803 2804 const uint64_t F32TwoE32 = 0x4F800000ULL; 2805 const uint64_t F32TwoE64 = 0x5F800000ULL; 2806 const uint64_t F32TwoE128 = 0x7F800000ULL; 2807 2808 APInt FF(32, 0); 2809 if (SrcVT == MVT::i32) 2810 FF = APInt(32, F32TwoE32); 2811 else if (SrcVT == MVT::i64) 2812 FF = APInt(32, F32TwoE64); 2813 else if (SrcVT == MVT::i128) 2814 FF = APInt(32, F32TwoE128); 2815 else 2816 llvm_unreachable("Unsupported UINT_TO_FP!"); 2817 2818 // Check whether the sign bit is set. 2819 SDValue Lo, Hi; 2820 GetExpandedInteger(Op, Lo, Hi); 2821 SDValue SignSet = DAG.getSetCC(dl, 2822 getSetCCResultType(Hi.getValueType()), 2823 Hi, DAG.getConstant(0, Hi.getValueType()), 2824 ISD::SETLT); 2825 2826 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2827 SDValue FudgePtr = DAG.getConstantPool( 2828 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 2829 TLI.getPointerTy()); 2830 2831 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2832 SDValue Zero = DAG.getIntPtrConstant(0); 2833 SDValue Four = DAG.getIntPtrConstant(4); 2834 if (TLI.isBigEndian()) std::swap(Zero, Four); 2835 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet, 2836 Zero, Four); 2837 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2838 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2839 Alignment = std::min(Alignment, 4u); 2840 2841 // Load the value out, extending it from f32 to the destination float type. 2842 // FIXME: Avoid the extend by constructing the right constant pool? 2843 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2844 FudgePtr, 2845 MachinePointerInfo::getConstantPool(), 2846 MVT::f32, 2847 false, false, Alignment); 2848 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2849 } 2850 2851 // Otherwise, use a libcall. 2852 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2853 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2854 "Don't know how to expand this UINT_TO_FP!"); 2855 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl); 2856 } 2857 2858 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) { 2859 SDLoc dl(N); 2860 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 2861 cast<AtomicSDNode>(N)->getMemoryVT(), 2862 N->getOperand(0), 2863 N->getOperand(1), N->getOperand(2), 2864 cast<AtomicSDNode>(N)->getMemOperand(), 2865 cast<AtomicSDNode>(N)->getOrdering(), 2866 cast<AtomicSDNode>(N)->getSynchScope()); 2867 return Swap.getValue(1); 2868 } 2869 2870 2871 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) { 2872 SDValue InOp0 = N->getOperand(0); 2873 EVT InVT = InOp0.getValueType(); 2874 2875 EVT OutVT = N->getValueType(0); 2876 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2877 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2878 unsigned OutNumElems = OutVT.getVectorNumElements(); 2879 EVT NOutVTElem = NOutVT.getVectorElementType(); 2880 2881 SDLoc dl(N); 2882 SDValue BaseIdx = N->getOperand(1); 2883 2884 SmallVector<SDValue, 8> Ops; 2885 Ops.reserve(OutNumElems); 2886 for (unsigned i = 0; i != OutNumElems; ++i) { 2887 2888 // Extract the element from the original vector. 2889 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), 2890 BaseIdx, DAG.getConstant(i, BaseIdx.getValueType())); 2891 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 2892 InVT.getVectorElementType(), N->getOperand(0), Index); 2893 2894 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext); 2895 // Insert the converted element to the new vector. 2896 Ops.push_back(Op); 2897 } 2898 2899 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2900 } 2901 2902 2903 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) { 2904 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 2905 EVT VT = N->getValueType(0); 2906 SDLoc dl(N); 2907 2908 unsigned NumElts = VT.getVectorNumElements(); 2909 SmallVector<int, 8> NewMask; 2910 for (unsigned i = 0; i != NumElts; ++i) { 2911 NewMask.push_back(SV->getMaskElt(i)); 2912 } 2913 2914 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 2915 SDValue V1 = GetPromotedInteger(N->getOperand(1)); 2916 EVT OutVT = V0.getValueType(); 2917 2918 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]); 2919 } 2920 2921 2922 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) { 2923 EVT OutVT = N->getValueType(0); 2924 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2925 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2926 unsigned NumElems = N->getNumOperands(); 2927 EVT NOutVTElem = NOutVT.getVectorElementType(); 2928 2929 SDLoc dl(N); 2930 2931 SmallVector<SDValue, 8> Ops; 2932 Ops.reserve(NumElems); 2933 for (unsigned i = 0; i != NumElems; ++i) { 2934 SDValue Op; 2935 // BUILD_VECTOR integer operand types are allowed to be larger than the 2936 // result's element type. This may still be true after the promotion. For 2937 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to 2938 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>. 2939 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem)) 2940 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i)); 2941 else 2942 Op = N->getOperand(i); 2943 Ops.push_back(Op); 2944 } 2945 2946 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2947 } 2948 2949 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) { 2950 2951 SDLoc dl(N); 2952 2953 assert(!N->getOperand(0).getValueType().isVector() && 2954 "Input must be a scalar"); 2955 2956 EVT OutVT = N->getValueType(0); 2957 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2958 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2959 EVT NOutVTElem = NOutVT.getVectorElementType(); 2960 2961 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0)); 2962 2963 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op); 2964 } 2965 2966 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) { 2967 SDLoc dl(N); 2968 2969 EVT OutVT = N->getValueType(0); 2970 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2971 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2972 2973 EVT InElemTy = OutVT.getVectorElementType(); 2974 EVT OutElemTy = NOutVT.getVectorElementType(); 2975 2976 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements(); 2977 unsigned NumOutElem = NOutVT.getVectorNumElements(); 2978 unsigned NumOperands = N->getNumOperands(); 2979 assert(NumElem * NumOperands == NumOutElem && 2980 "Unexpected number of elements"); 2981 2982 // Take the elements from the first vector. 2983 SmallVector<SDValue, 8> Ops(NumOutElem); 2984 for (unsigned i = 0; i < NumOperands; ++i) { 2985 SDValue Op = N->getOperand(i); 2986 for (unsigned j = 0; j < NumElem; ++j) { 2987 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 2988 InElemTy, Op, DAG.getConstant(j, 2989 TLI.getVectorIdxTy())); 2990 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext); 2991 } 2992 } 2993 2994 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2995 } 2996 2997 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) { 2998 EVT OutVT = N->getValueType(0); 2999 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 3000 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 3001 3002 EVT NOutVTElem = NOutVT.getVectorElementType(); 3003 3004 SDLoc dl(N); 3005 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 3006 3007 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl, 3008 NOutVTElem, N->getOperand(1)); 3009 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, 3010 V0, ConvElem, N->getOperand(2)); 3011 } 3012 3013 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) { 3014 SDLoc dl(N); 3015 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 3016 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, TLI.getVectorIdxTy()); 3017 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3018 V0->getValueType(0).getScalarType(), V0, V1); 3019 3020 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming 3021 // element types. If this is the case then we need to expand the outgoing 3022 // value and not truncate it. 3023 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0)); 3024 } 3025 3026 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) { 3027 SDLoc dl(N); 3028 unsigned NumElems = N->getNumOperands(); 3029 3030 EVT RetSclrTy = N->getValueType(0).getVectorElementType(); 3031 3032 SmallVector<SDValue, 8> NewOps; 3033 NewOps.reserve(NumElems); 3034 3035 // For each incoming vector 3036 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) { 3037 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx)); 3038 EVT SclrTy = Incoming->getValueType(0).getVectorElementType(); 3039 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements(); 3040 3041 for (unsigned i=0; i<NumElem; ++i) { 3042 // Extract element from incoming vector 3043 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, 3044 Incoming, DAG.getConstant(i, TLI.getVectorIdxTy())); 3045 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex); 3046 NewOps.push_back(Tr); 3047 } 3048 } 3049 3050 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), 3051 &NewOps[0], NewOps.size()); 3052 } 3053