| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
33 cl::desc("Align ARM NEON spills in prolog and epilog"));
67 // stack frame. ARM (especially Thumb) has small immediate offset to
96 if (MI->getOpcode() == ARM::LDMIA_RET ||
97 MI->getOpcode() == ARM::t2LDMIA_RET ||
98 MI->getOpcode() == ARM::LDMIA_UPD ||
99 MI->getOpcode() == ARM::t2LDMIA_UPD ||
100 MI->getOpcode() == ARM::VLDMDIA_UPD) {
108 if ((MI->getOpcode() == ARM::LDR_POST_IMM |
[all...] |
| /bionic/ |
| ABI-bugs.txt | 8 sigset_t is too small on ARM and x86 (but correct on MIPS), so support
15 dlclose(3); this only affects ARM. http://b/4998315
|
| /external/chromium_org/build/android/tests/symbolize/ |
| Makefile | 5 TOOLCHAIN=../../../../third_party/android_tools/ndk/toolchains/arm-linux-androideabi-4.6/prebuilt/linux-x86_64/bin/arm-linux-androideabi-
|
| /external/chromium_org/build/linux/ |
| install-arm-sysroot.py | 6 # Script to install ARM root image for cross building of ARM chrome on linux.
12 # state or precise/arm but for consistency we currently use a pre-built root
34 # or if GYP_DEFINES doesn't include target_arch=arm
38 if "target_arch=arm" not in os.environ.get('GYP_DEFINES', ''):
42 sysroot = os.path.join(src_root, 'arm-sysroot')
49 print "ARM root image already up-to-date: %s" % sysroot
52 print "Installing ARM root image: %s" % sysroot
|
| /external/chromium_org/ppapi/native_client/src/trusted/plugin/arch_arm/ |
| sandbox_isa.cc | 8 // The list of supported ISA strings for ARM. See issue:
11 const char* const kNexeArchARM = "arm";
|
| /external/clang/test/CodeGen/ |
| pr5406.c | 1 // REQUIRES: arm-registered-target
2 // RUN: %clang_cc1 %s -emit-llvm -triple arm-apple-darwin -o - | FileCheck %s
|
| /external/compiler-rt/lib/interception/ |
| CMakeLists.txt | 21 add_library(RTInterception.arm.android OBJECT ${INTERCEPTION_SOURCES})
22 set_target_compile_flags(RTInterception.arm.android
|
| /external/kernel-headers/original/asm-arm/ |
| ide.h | 2 * linux/include/asm-arm/ide.h
8 * This file contains the ARM architecture specific IDE code.
|
| /external/llvm/test/CodeGen/AArch64/ |
| neon-rounding-shift.ll | 3 declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>)
4 declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>)
8 %tmp1 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
15 %tmp1 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
20 declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>)
21 declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>)
25 %tmp1 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
32 %tmp1 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
37 declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>)
38 declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>
[all...] |
| neon-saturating-rounding-shift.ll | 3 declare <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8>, <8 x i8>)
4 declare <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8>, <8 x i8>)
8 %tmp1 = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
15 %tmp1 = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
20 declare <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8>, <16 x i8>)
21 declare <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8>, <16 x i8>)
25 %tmp1 = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
32 %tmp1 = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
37 declare <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16>, <4 x i16>)
38 declare <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16>, <4 x i16>
[all...] |
| neon-saturating-shift.ll | 3 declare <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8>, <8 x i8>)
4 declare <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8>, <8 x i8>)
8 %tmp1 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
15 %tmp1 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
20 declare <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8>, <16 x i8>)
21 declare <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8>, <16 x i8>)
25 %tmp1 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
32 %tmp1 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
37 declare <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16>, <4 x i16>)
38 declare <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16>, <4 x i16>
[all...] |
| neon-shift.ll | 3 declare <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8>, <8 x i8>)
4 declare <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8>, <8 x i8>)
8 %tmp1 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
15 %tmp1 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
20 declare <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8>, <16 x i8>)
21 declare <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8>, <16 x i8>)
25 %tmp1 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
32 %tmp1 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
37 declare <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16>, <4 x i16>)
38 declare <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16>, <4 x i16>
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| 2009-09-09-fpcmp-ole.ll | 1 ; RUN: llc -O1 -march=arm -mattr=+vfp2 -mtriple=arm-linux-gnueabi < %s | FileCheck %s
|
| 2009-10-27-double-align.ll | 1 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
2 ; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=basic | FileCheck %s
|
| arm-frameaddr.ll | 1 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
2 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=LINUX
|
| elf-lcomm-align.ll | 1 ; RUN: llc < %s -mtriple=arm-linux-gnueabi -O0 | FileCheck %s
2 ; run with -O0 to avoid arm global merging.
|
| fast-isel-GEP-coalesce.ll | 1 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
14 ; ARM: t1
18 ; ARM: add r0, r0, #124
26 ; ARM: t2
30 ; ARM: movw [[R:r[0-9]+]], #1148
31 ; ARM: add r0, r{{[0-9]+}}, [[R]]
39 ; ARM: t3
43 ; ARM: add r0, r0, #140
51 ; ARM: t
[all...] |
| fast-isel-cmp-imm.ll | 1 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
2 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
7 ; ARM: t1a
10 ; ARM: vcmpe.f32 s{{[0-9]+}}, #0
27 ; ARM: t1b
30 ; ARM: vldr
31 ; ARM: vcmpe.f32 s{{[0-9]+}}, s{{[0-9]+}}
46 ; ARM: t2a
49 ; ARM: vcmpe.f64 d{{[0-9]+}}, #0
64 ; ARM: t2
[all...] |
| fnmul.ll | 1 ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep vnmul.f64
2 ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math | grep vmul.f64
|
| insn-sched1.ll | 1 ; RUN: llc < %s -march=arm -mattr=+v6
2 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6 |\
|
| mul.ll | 1 ; RUN: llc < %s -march=arm | grep mul | count 2
2 ; RUN: llc < %s -march=arm | grep lsl | count 2
|
| str_trunc.ll | 1 ; RUN: llc < %s -march=arm | \
3 ; RUN: llc < %s -march=arm | \
|
| unord.ll | 1 ; RUN: llc < %s -march=arm | grep movne | count 1
2 ; RUN: llc < %s -march=arm | grep moveq | count 1
|
| vcvt-v8.ll | 6 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1)
14 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %tmp1)
22 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1)
30 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %tmp1)
38 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1)
46 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %tmp1)
54 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1)
62 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %tmp1)
70 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1)
78 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %tmp1
[all...] |
| /external/llvm/test/Object/ARM/ |
| symbol-addr.ll | 1 ; RUN: llc %s -mtriple=arm-unknown-unknown -filetype=obj -o - \
6 ; Check that the symbol address does not include the ARM/Thumb instruction
|
