| /external/llvm/test/MC/ARM/ |
| vfp4.s | 1 @ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=ARM
5 @ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee]
9 @ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee]
14 @ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2]
18 @ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2]
22 @ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee]
26 @ ARM: vfnma.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0x92,0xee]
31 @ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee]
35 @ ARM: vfms.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0xa2,0xee]
40 @ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
15 #include "ARM.h"
47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti),
48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
49 BasePtr(ARM::R6) {
107 Reserved.set(ARM::SP);
108 Reserved.set(ARM::PC)
[all...] |
| /bionic/libstdc++/src/ |
| one_time_construction.cpp | 12 // constructors as defined in the "Run-time ABI for the ARM Architecture"
15 // ARM C++ ABI and Itanium/x86 C++ ABI has different definition for
18 // ARM C++ ABI defines the LSB of guard variable should be tested
24 // Meanwhile, guard variable are 32bit aligned for ARM, and 64bit
29 // section 3.2.3 of ARM IHI 0041C (for ARM)
37 // The ARM C++ ABI mandates that guard variable are
51 #else // GCC sources indicates all none-arm follow the same ABI
|
| /dalvik/vm/mterp/x86/ |
| alt_stub.S | 4 * handler. Unlike the Arm handler, we can't do this as a tail call
7 * Note that unlike in the Arm implementation, we should never arrive
|
| /external/clang/include/clang/Basic/ |
| CMakeLists.txt | 31 # ARM NEON
32 clang_tablegen(arm_neon.inc -gen-arm-neon-sema
|
| /external/compiler-rt/ |
| Android.mk | 152 # ARM-specific runtimes
154 lib/arm/aeabi_dcmp.S \
155 lib/arm/aeabi_fcmp.S \
156 lib/arm/aeabi_idivmod.S \
157 lib/arm/aeabi_ldivmod.S \
158 lib/arm/aeabi_memcmp.S \
159 lib/arm/aeabi_memcpy.S \
160 lib/arm/aeabi_memmove.S \
161 lib/arm/aeabi_memset.S \
162 lib/arm/aeabi_uidivmod.S
[all...] |
| /external/llvm/cmake/platforms/ |
| Android.cmake | 25 SET(ANDROID_COMMON_FLAGS "-target arm-linux-androideabi --sysroot=${LLVM_ANDROID_TOOLCHAIN_DIR}/sysroot -B${LLVM_ANDROID_TOOLCHAIN_DIR} -mllvm -arm-enable-ehabi")
|
| /external/llvm/docs/ |
| HowToBuildOnARM.rst | 2 How To Build On ARM
9 Clang on ARM.
11 Notes On Building LLVM/Clang on ARM
13 Here are some notes on building/testing LLVM/Clang on ARM. Note that
14 ARM encompasses a wide variety of CPUs; this advice is primarily based
17 #. If you are building LLVM/Clang on an ARM board with 1G of memory or less,
32 #. The most popular linaro/ubuntu OS's for ARM boards, eg, the
43 --enable-targets=arm --enable-optimized --enable-assertions
|
| /external/llvm/test/CodeGen/ARM/ |
| 2011-08-12-vmovqqqq-pseudo.ll | 7 %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2)
12 declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
|
| 2012-05-04-vmov.ll | 1 ; RUN: llc -O1 -march=arm -mcpu=cortex-a9 < %s | FileCheck -check-prefix=A9-CHECK %s
2 ; RUN: llc -O1 -march=arm -mcpu=swift < %s | FileCheck -check-prefix=SWIFT-CHECK %s
|
| 2012-08-30-select.ll | 10 %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1)
17 declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* , i32 )
|
| 2013-05-13-AAPCS-byval-padding.ll | 1 ;PR15293: ARM codegen ice - expected larger existing stack allocation
2 ;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
|
| 2013-05-13-AAPCS-byval-padding2.ll | 1 ;PR15293: ARM codegen ice - expected larger existing stack allocation
2 ;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
|
| ehabi-no-landingpad.ll | 2 ; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors | FileCheck %s
|
| fast-isel-pic.ll | 2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
19 ; ARM: LoadGV
20 ; ARM: ldr [[reg1:r[0-9]+]],
21 ; ARM: add [[reg1]], pc, [[reg1]]
47 ; ARM: LoadIndirectSymbol
48 ; ARM: ldr [[reg4:r[0-9]+]],
49 ; ARM: ldr [[reg4]], [pc, [[reg4]]]
|
| fpowi.ll | 1 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep powidf2
6 target triple = "arm-unknown-linux-gnueabi"
|
| hidden-vis.ll | 1 ; RUN: llc < %s -mtriple=arm-linux | FileCheck %s -check-prefix=LINUX
2 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
|
| ifcvt1.ll | 1 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
2 ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s -check-prefix=SWIFT
|
| illegal-vector-bitcast.ll | 1 ; RUN: llc < %s -march=arm
2 ; RUN: llc < %s -mtriple=arm-linux
|
| indirectbr.ll | 1 ; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM
9 ; ARM-LABEL: foo:
16 ; ARM: bx
23 ; ARM: bx
51 ; ARM: ldr [[R1:r[0-9]+]], LCPI
52 ; ARM: add [[R1b:r[0-9]+]], pc, [[R1]]
53 ; ARM: str [[R1b]]
64 ; ARM: .long Ltmp0-(LPC{{.*}}+8)
|
| truncstore-dag-combine.ll | 1 ; RUN: llc < %s -march=arm -mattr=+v4t | not grep orr
2 ; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov
|
| tst_teq.ll | 1 ; RUN: llc < %s -march=arm | grep tst
2 ; RUN: llc < %s -march=arm | grep teq
|
| unsafe-fsub.ll | 1 ; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck -check-prefix=SAFE %s
2 ; RUN: llc -march=arm -mcpu=cortex-a9 -enable-unsafe-fp-math < %s | FileCheck -check-prefix=FAST %s
|
| vminmaxnm.ll | 8 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
17 %tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
26 %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
35 %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
39 declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
40 declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
41 declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
42 declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
|
| /external/llvm/test/CodeGen/Generic/ |
| 2011-07-07-ScheduleDAGCrash.ll | 6 ; The ARM backend can't handle i256 math at the moment.
7 ; XFAIL: arm
|
