1 //==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Class definitions. 12 //===----------------------------------------------------------------------===// 13 14 class SystemZReg<string n> : Register<n> { 15 let Namespace = "SystemZ"; 16 } 17 18 class SystemZRegWithSubregs<string n, list<Register> subregs> 19 : RegisterWithSubRegs<n, subregs> { 20 let Namespace = "SystemZ"; 21 } 22 23 let Namespace = "SystemZ" in { 24 def subreg_32bit : SubRegIndex<32>; // could also be named "subreg_high32" 25 // Indices are used in a variety of ways, so don't set an Offset. 26 def subreg_high : SubRegIndex<64, -1>; 27 def subreg_low : SubRegIndex<64, -1>; 28 def subreg_low32 : ComposedSubRegIndex<subreg_low, subreg_32bit>; 29 } 30 31 // Define a register class that contains values of type TYPE and an 32 // associated operand called NAME. SIZE is the size and alignment 33 // of the registers and REGLIST is the list of individual registers. 34 multiclass SystemZRegClass<string name, ValueType type, int size, dag regList> { 35 def AsmOperand : AsmOperandClass { 36 let Name = name; 37 let ParserMethod = "parse"##name; 38 let RenderMethod = "addRegOperands"; 39 } 40 def Bit : RegisterClass<"SystemZ", [type], size, regList> { 41 let Size = size; 42 } 43 def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> { 44 let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand"); 45 } 46 } 47 48 //===----------------------------------------------------------------------===// 49 // General-purpose registers 50 //===----------------------------------------------------------------------===// 51 52 // Lower 32 bits of one of the 16 64-bit general-purpose registers 53 class GPR32<bits<16> num, string n> : SystemZReg<n> { 54 let HWEncoding = num; 55 } 56 57 // One of the 16 64-bit general-purpose registers. 58 class GPR64<bits<16> num, string n, GPR32 low> 59 : SystemZRegWithSubregs<n, [low]> { 60 let HWEncoding = num; 61 let SubRegIndices = [subreg_32bit]; 62 } 63 64 // 8 even-odd pairs of GPR64s. 65 class GPR128<bits<16> num, string n, GPR64 high, GPR64 low> 66 : SystemZRegWithSubregs<n, [high, low]> { 67 let HWEncoding = num; 68 let SubRegIndices = [subreg_high, subreg_low]; 69 } 70 71 // General-purpose registers 72 foreach I = 0-15 in { 73 def R#I#W : GPR32<I, "r"#I>; 74 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"W")>, DwarfRegNum<[I]>; 75 } 76 77 foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in { 78 def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#I#"D"), 79 !cast<GPR64>("R"#!add(I, 1)#"D")>; 80 } 81 82 /// Allocate the callee-saved R6-R13 backwards. That way they can be saved 83 /// together with R14 and R15 in one prolog instruction. 84 defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uW", 0, 5), 85 (sequence "R%uW", 15, 6))>; 86 defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD", 0, 5), 87 (sequence "R%uD", 15, 6))>; 88 89 // The architecture doesn't really have any i128 support, so model the 90 // register pairs as untyped instead. 91 defm GR128 : SystemZRegClass<"GR128", untyped, 128, (add R0Q, R2Q, R4Q, 92 R12Q, R10Q, R8Q, R6Q, 93 R14Q)>; 94 95 // Base and index registers. Everything except R0, which in an address 96 // context evaluates as 0. 97 defm ADDR32 : SystemZRegClass<"ADDR32", i32, 32, (sub GR32Bit, R0W)>; 98 defm ADDR64 : SystemZRegClass<"ADDR64", i64, 64, (sub GR64Bit, R0D)>; 99 100 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs 101 // of a GR128. 102 defm ADDR128 : SystemZRegClass<"ADDR128", untyped, 128, (sub GR128Bit, R0Q)>; 103 104 //===----------------------------------------------------------------------===// 105 // Floating-point registers 106 //===----------------------------------------------------------------------===// 107 108 // Lower 32 bits of one of the 16 64-bit floating-point registers 109 class FPR32<bits<16> num, string n> : SystemZReg<n> { 110 let HWEncoding = num; 111 } 112 113 // One of the 16 64-bit floating-point registers 114 class FPR64<bits<16> num, string n, FPR32 low> 115 : SystemZRegWithSubregs<n, [low]> { 116 let HWEncoding = num; 117 let SubRegIndices = [subreg_32bit]; 118 } 119 120 // 8 pairs of FPR64s, with a one-register gap inbetween. 121 class FPR128<bits<16> num, string n, FPR64 high, FPR64 low> 122 : SystemZRegWithSubregs<n, [high, low]> { 123 let HWEncoding = num; 124 let SubRegIndices = [subreg_high, subreg_low]; 125 } 126 127 // Floating-point registers 128 foreach I = 0-15 in { 129 def F#I#S : FPR32<I, "f"#I>; 130 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>, 131 DwarfRegNum<[!add(I, 16)]>; 132 } 133 134 foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in { 135 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#I#"D"), 136 !cast<FPR64>("F"#!add(I, 2)#"D")>; 137 } 138 139 // There's no store-multiple instruction for FPRs, so we're not fussy 140 // about the order in which call-saved registers are allocated. 141 defm FP32 : SystemZRegClass<"FP32", f32, 32, (sequence "F%uS", 0, 15)>; 142 defm FP64 : SystemZRegClass<"FP64", f64, 64, (sequence "F%uD", 0, 15)>; 143 defm FP128 : SystemZRegClass<"FP128", f128, 128, (add F0Q, F1Q, F4Q, F5Q, 144 F8Q, F9Q, F12Q, F13Q)>; 145 146 //===----------------------------------------------------------------------===// 147 // Other registers 148 //===----------------------------------------------------------------------===// 149 150 // The 2-bit condition code field of the PSW. Every register named in an 151 // inline asm needs a class associated with it. 152 def CC : SystemZReg<"cc">; 153 def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>; 154
