| /external/llvm/include/llvm/IR/ |
| Instruction.h | 103 return Opcode >= Shl && Opcode <= AShr;
114 return getOpcode() == AShr;
|
| Operator.h | 154 OpC == Instruction::AShr ||
349 : public ConcreteOperator<PossiblyExactOperator, Instruction::AShr> {
|
| InstrTypes.h | 276 DEFINE_HELPERS(AShr, Exact) // CreateExactAShr
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 319 if (I.getOpcode() != Instruction::AShr &&
337 if (I.getOpcode() != Instruction::AShr)
339 // ashr i32 X, 32 --> ashr i32 X, 31
362 // If 'shift2' is an ashr, we would have to get the sign bit into a funny
506 if (isValid && I.getOpcode() == Instruction::AShr)
554 // If this is oversized composite shift, then unsigned shifts get 0, ashr
557 if (I.getOpcode() != Instruction::AShr)
559 AmtSum = TypeBits-1; // Saturate to 31 for i32 ashr.
584 ShiftOp->getOpcode() == Instruction::AShr);
[all...] |
| InstCombineSelect.cpp | 95 case Instruction::AShr:
113 case Instruction::AShr:
540 Value *AShr = Builder->CreateAShr(CmpLHS, Ty->getBitWidth()-1);
544 return ReplaceInstUsesWith(SI, Builder->CreateOr(AShr, C1));
546 Value *And = Builder->CreateAnd(AShr, C2->getValue()-C1->getValue());
[all...] |
| InstCombineVectorOps.cpp | 530 case Instruction::AShr:
593 case Instruction::AShr:
690 case Instruction::AShr:
[all...] |
| InstCombineCompares.cpp | [all...] |
| InstCombineSimplifyDemanded.cpp | 655 case Instruction::AShr:
667 // If the sign bit is the only bit demanded by this ashr, then there is no
[all...] |
| /external/llvm/unittests/Transforms/Utils/ |
| IntegerDivision.cpp | 46 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr);
106 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr);
|
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 137 case Instruction::AShr:
|
| InstructionSimplify.cpp | [all...] |
| ValueTracking.cpp | 512 case Instruction::AShr:
513 // (ashr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
[all...] |
| /external/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCUtil.cpp | 221 case Instruction::Shl: case Instruction::LShr: case Instruction::AShr:
|
| /external/llvm/include/llvm/Support/ |
| PatternMatch.h | 496 inline BinaryOp_match<LHS, RHS, Instruction::AShr>
498 return BinaryOp_match<LHS, RHS, Instruction::AShr>(L, R);
525 /// m_Shr - Matches LShr or AShr.
527 inline BinOp2_match<LHS, RHS, Instruction::LShr, Instruction::AShr>
529 return BinOp2_match<LHS, RHS, Instruction::LShr, Instruction::AShr>(L, R);
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopRotation.cpp | 193 case Instruction::AShr:
|
| /external/llvm/lib/IR/ |
| ConstantFold.cpp | [all...] |
| Instruction.cpp | 247 case AShr: return "ashr";
|
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/CppBackend/ |
| CPPBackend.cpp | [all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | 749 case Instruction::AShr:
863 case Instruction::AShr:
[all...] |
| /external/llvm/lib/AsmParser/ |
| LLLexer.cpp | 648 INSTKEYWORD(shl, Shl); INSTKEYWORD(lshr, LShr); INSTKEYWORD(ashr, AShr);
|
| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 349 case 9: {Op = Instruction::AShr; break; }
|
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | 150 case bitc::BINOP_ASHR: return Instruction::AShr;
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | 202 case bitc::BINOP_ASHR: return Instruction::AShr;
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | 444 case bitc::BINOP_ASHR: return Instruction::AShr;
[all...] |
