| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 167 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
284 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
287 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
290 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
353 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
398 baseReg = MCOperand::CreateReg(X86::x); break;
403 baseReg = MCOperand::CreateReg(0);
444 indexReg = MCOperand::CreateReg(X86::x); break;
453 indexReg = MCOperand::CreateReg(0);
470 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 33 Inst.addOperand(MCOperand::CreateReg(Reg));
|
| MCInst.h | 111 static MCOperand CreateReg(unsigned Reg) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 41 NopInst.addOperand(MCOperand::CreateReg(0));
44 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
47 NopInst.addOperand(MCOperand::CreateReg(0));
48 NopInst.addOperand(MCOperand::CreateReg(0));
|
| Thumb1InstrInfo.cpp | 31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
34 NopInst.addOperand(MCOperand::CreateReg(0));
|
| ARMAsmPrinter.cpp | [all...] |
| ARMMCInstLower.cpp | 75 MCOp = MCOperand::CreateReg(MO.getReg());
|
| Thumb2ITBlockPass.cpp | 185 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
210 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 347 Inst.addOperand(MCOperand::CreateReg(Reg));
358 Inst.addOperand(MCOperand::CreateReg(Reg));
377 Inst.addOperand(MCOperand::CreateReg(Reg));
389 Inst.addOperand(MCOperand::CreateReg(Reg));
400 Inst.addOperand(MCOperand::CreateReg(Reg));
411 Inst.addOperand(MCOperand::CreateReg(Reg));
427 Inst.addOperand(MCOperand::CreateReg(Reg));
430 Inst.addOperand(MCOperand::CreateReg(Reg));
431 Inst.addOperand(MCOperand::CreateReg(Base));
448 Inst.addOperand(MCOperand::CreateReg(Reg))
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 277 Inst.addOperand(MCOperand::CreateReg(getReg()));
299 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
349 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
379 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
453 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
454 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
540 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
541 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
548 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
549 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 64 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
72 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
80 MO.push_back(MachineOperand::CreateReg(0, false, false,
|
| X86MCInstLower.cpp | 350 MCOp = MCOperand::CreateReg(MO.getReg());
601 OutMI.addOperand(MCOperand::CreateReg(X86::R10));
602 OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
645 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
646 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
648 LEA.addOperand(MCOperand::CreateReg(0)); // index
650 LEA.addOperand(MCOperand::CreateReg(0)); // seg
653 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
654 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
656 LEA.addOperand(MCOperand::CreateReg(0)); // inde
[all...] |
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 59 Inst.addOperand(MCOperand::CreateReg(RegNo));
190 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
200 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
211 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
213 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
223 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
225 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
235 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.cpp | 51 MCOp = MCOperand::CreateReg(MO.getReg());
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUMCInstLower.cpp | 54 MCOp = MCOperand::CreateReg(MO.getReg());
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.cpp | 51 MCOp = MCOperand::CreateReg(MO.getReg());
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 252 Inst.addOperand(MCOperand::CreateReg(Register));
263 Inst.addOperand(MCOperand::CreateReg(Register));
274 Inst.addOperand(MCOperand::CreateReg(Register));
285 Inst.addOperand(MCOperand::CreateReg(Register));
296 Inst.addOperand(MCOperand::CreateReg(Register));
307 Inst.addOperand(MCOperand::CreateReg(Register));
319 Inst.addOperand(MCOperand::CreateReg(Register));
330 Inst.addOperand(MCOperand::CreateReg(Register));
342 Inst.addOperand(MCOperand::CreateReg(Register));
353 Inst.addOperand(MCOperand::CreateReg(Register))
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 141 unsigned CreateReg(MVT VT);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMCInstLower.cpp | 58 MCO = MCOperand::CreateReg(MO.getReg());
|
| HexagonPeephole.cpp | 223 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
230 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430MCInstLower.cpp | 123 MCOp = MCOperand::CreateReg(MO.getReg());
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZMCInstLower.cpp | 60 return MCOperand::CreateReg(MO.getReg());
|
| /external/llvm/lib/Target/XCore/ |
| XCoreMCInstLower.cpp | 90 return MCOperand::CreateReg(MO.getReg());
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64MCInstLower.cpp | 107 MCOp = MCOperand::CreateReg(MO.getReg());
|
