1 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Thumb1InstrInfo.h" 15 #include "ARM.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineInstrBuilder.h" 18 #include "llvm/CodeGen/MachineMemOperand.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/MC/MCInst.h" 21 22 using namespace llvm; 23 24 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) 25 : ARMBaseInstrInfo(STI), RI(STI) { 26 } 27 28 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 29 void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 30 NopInst.setOpcode(ARM::tMOVr); 31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 33 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 34 NopInst.addOperand(MCOperand::CreateReg(0)); 35 } 36 37 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { 38 return 0; 39 } 40 41 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 42 MachineBasicBlock::iterator I, DebugLoc DL, 43 unsigned DestReg, unsigned SrcReg, 44 bool KillSrc) const { 45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 46 .addReg(SrcReg, getKillRegState(KillSrc))); 47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 48 "Thumb1 can only copy GPR registers"); 49 } 50 51 void Thumb1InstrInfo:: 52 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 53 unsigned SrcReg, bool isKill, int FI, 54 const TargetRegisterClass *RC, 55 const TargetRegisterInfo *TRI) const { 56 assert((RC == &ARM::tGPRRegClass || 57 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 58 isARMLowRegister(SrcReg))) && "Unknown regclass!"); 59 60 if (RC == &ARM::tGPRRegClass || 61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 62 isARMLowRegister(SrcReg))) { 63 DebugLoc DL; 64 if (I != MBB.end()) DL = I->getDebugLoc(); 65 66 MachineFunction &MF = *MBB.getParent(); 67 MachineFrameInfo &MFI = *MF.getFrameInfo(); 68 MachineMemOperand *MMO = 69 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 70 MachineMemOperand::MOStore, 71 MFI.getObjectSize(FI), 72 MFI.getObjectAlignment(FI)); 73 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi)) 74 .addReg(SrcReg, getKillRegState(isKill)) 75 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 76 } 77 } 78 79 void Thumb1InstrInfo:: 80 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 81 unsigned DestReg, int FI, 82 const TargetRegisterClass *RC, 83 const TargetRegisterInfo *TRI) const { 84 assert((RC == &ARM::tGPRRegClass || 85 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 86 isARMLowRegister(DestReg))) && "Unknown regclass!"); 87 88 if (RC == &ARM::tGPRRegClass || 89 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 90 isARMLowRegister(DestReg))) { 91 DebugLoc DL; 92 if (I != MBB.end()) DL = I->getDebugLoc(); 93 94 MachineFunction &MF = *MBB.getParent(); 95 MachineFrameInfo &MFI = *MF.getFrameInfo(); 96 MachineMemOperand *MMO = 97 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 98 MachineMemOperand::MOLoad, 99 MFI.getObjectSize(FI), 100 MFI.getObjectAlignment(FI)); 101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) 102 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 103 } 104 } 105
