| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 154 void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
155 if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
156 LIS.removeInterval(Reg);
164 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg),
203 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
212 DefMI->addRegisterDead(LI->reg, 0);
251 unsigned Reg = MOI->getReg();
252 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
254 if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
[all...] |
| MachineCopyPropagation.cpp | 51 void SourceNoLongerAvailable(unsigned Reg,
65 MachineCopyPropagation::SourceNoLongerAvailable(unsigned Reg,
68 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
241 unsigned Reg = MO.getReg();
242 if (!Reg)
245 if (TargetRegisterInfo::isVirtualRegister(Reg))
250 Defs.push_back(Reg);
254 // If 'Reg' is defined by a copy, the copy is no longer a candidate
256 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
273 unsigned Reg = (*DI)->getOperand(0).getReg()
[all...] |
| RegisterScavenging.cpp | 17 #define DEBUG_TYPE "reg-scavenging"
33 void RegScavenger::setUsed(unsigned Reg) {
34 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
39 bool RegScavenger::isAliasUsed(unsigned Reg) const {
40 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
41 if (isUsed(*AI, *AI == Reg))
49 I->Reg = 0;
106 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
107 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
132 unsigned Reg = MO.getReg()
[all...] |
| TargetRegisterInfo.cpp | 37 if (!Reg)
39 else if (TargetRegisterInfo::isStackSlot(Reg))
40 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
41 else if (TargetRegisterInfo::isVirtualRegister(Reg))
42 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
43 else if (TRI && Reg < TRI->getNumRegs())
44 OS << '%' << TRI->getName(Reg);
46 OS << "%physreg" << Reg;
103 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
104 assert(isPhysicalRegister(reg) && "reg must be a physical register")
[all...] |
| TargetSchedule.cpp | 265 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
268 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
|
| VirtRegMap.cpp | 119 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
120 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
121 OS << '[' << PrintReg(Reg, TRI) << " -> "
122 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
123 << MRI->getRegClass(Reg)->getName() << "\n";
128 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
129 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
130 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
131 << "] " << MRI->getRegClass(Reg)->getName() << "\n"
[all...] |
| CriticalAntiDepBreaker.cpp | 66 unsigned Reg = *AI;
67 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
68 KillIndices[Reg] = BBSize;
69 DefIndices[Reg] = ~0u;
81 unsigned Reg = *AI;
82 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
83 KillIndices[Reg] = BBSize;
84 DefIndices[Reg] = ~0u;
100 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg)
[all...] |
| MachineInstrBundle.cpp | 133 unsigned Reg = MO.getReg();
134 if (!Reg)
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 if (LocalDefSet.count(Reg)) {
141 KilledDefSet.insert(Reg);
143 if (ExternUseSet.insert(Reg)) {
144 ExternUses.push_back(Reg);
146 UndefUseSet.insert(Reg);
150 KilledUseSet.insert(Reg);
156 unsigned Reg = MO.getReg()
[all...] |
| MachineRegisterInfo.cpp | 43 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
45 VRegInfo[Reg].first = RC;
49 MachineRegisterInfo::constrainRegClass(unsigned Reg,
52 const TargetRegisterClass *OldRC = getRegClass(Reg);
61 setRegClass(Reg, NewRC);
66 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
68 const TargetRegisterClass *OldRC = getRegClass(Reg);
77 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
93 setRegClass(Reg, NewRC);
107 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs())
[all...] |
| MachineSink.cpp | 89 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
94 bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
156 MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
161 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
165 if (MRI->use_nodbg_empty(Reg))
185 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
199 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
312 unsigned Reg = MO.getReg();
313 if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg))
[all...] |
| PeepholeOptimizer.cpp | 324 unsigned Reg = MO.getReg();
325 if (!Reg)
328 Def = Reg;
333 Src = Reg;
351 unsigned Reg = MO.getReg();
352 if (!Reg)
359 SrcSrc = Reg;
425 unsigned Reg = MI->getOperand(0).getReg();
430 TargetRegisterInfo::isVirtualRegister(Reg) &&
431 MRI->hasOneUse(Reg)) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 98 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
174 // Create the reg, emit the copy.
199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
200 if (TargetRegisterInfo::isVirtualRegister(Reg))
201 return Reg;
215 // If the specific node value is only used by a CopyToReg and the dest reg
236 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
237 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
238 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
240 VRBase = Reg;
[all...] |
| ScheduleDAGSDNodes.cpp | 117 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
118 if (TargetRegisterInfo::isVirtualRegister(Reg))
125 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
126 PhysReg = Reg;
128 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
527 // Check for phys reg copy.
635 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
636 if (TargetRegisterInfo::isVirtualRegister(Reg))
649 dbgs() << "PHYS REG COPY\n";
768 unsigned Reg = 0
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 196 unsigned Reg = CSI[i-1].getReg();
198 MBB.addLiveIn(Reg);
200 .addReg(Reg, RegState::Kill);
|
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.cpp | 247 unsigned Reg = MO.getReg();
248 if (Reg == AMDGPU::ALU_CONST) {
270 unsigned Reg = MI->getOperand(SrcIdx).getReg();
271 if (Reg == AMDGPU::ALU_CONST) {
277 if (Reg == AMDGPU::ALU_LITERAL_X) {
298 unsigned Reg = Srcs[i].first->getReg();
299 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
300 if (Reg == AMDGPU::OQAP) {
303 if (PV.find(Reg) != PV.end()) {
304 // 255 is used to tells its a PS/PV reg
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 38 /// Target machine description which we query for reg. names, data
72 unsigned Reg);
241 unsigned Reg = MO.getReg();
244 // check whether Reg is defined or used before delay slot.
245 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
249 // check whether Reg is defined before delay slot.
250 if (IsRegInSet(RegDefs, Reg))
271 const MachineOperand &Reg = MI->getOperand(0);
272 assert(Reg.isReg() && "JMPL first operand is not a register.")
363 unsigned reg = AddMI->getOperand(0).getReg(); local
391 unsigned reg = OrMI->getOperand(0).getReg(); local
429 unsigned reg = SetHiMI->getOperand(0).getReg(); local
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 182 unsigned Reg = MO.getReg();
183 if (X86II::isX86_64NonExtLowByteReg(Reg))
534 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
541 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
549 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 153 unsigned Reg = MI.getOperand(0).getReg();
156 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
172 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
178 .addReg(Reg, getKillRegState(isKill))
183 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
193 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
199 .addReg(Reg, getKillRegState(isKill))
204 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
222 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
228 .addReg(Reg, getKillRegState(isKill)
[all...] |
| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.cpp | 27 enum MapKind { Operand, Imm, Reg };
32 Record *Reg; // Physical register.
82 OperandMap[BaseIdx + i].Kind = OpData::Reg;
83 OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
239 case OpData::Reg: {
240 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
243 if (Reg->getName() == "zero_reg")
246 o << Reg->getValueAsString("Namespace") << "::" << Reg->getName()
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
263 if (!MRI.isLiveOut(Reg)) {
264 MRI.addLiveOut(Reg);
266 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
|
| R600InstrInfo.cpp | 349 unsigned Reg = MI->getOperand(idx).getReg();
350 switch (Reg) {
|
| SIISelLowering.cpp | 367 unsigned Reg = dstClass->getRegister(SGPRIndex);
369 DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineTraceMetrics.h | 121 unsigned Reg;
127 LiveInReg(unsigned Reg, unsigned Height = 0) : Reg(Reg), Height(Height) {}
|
| ScheduleDAGInstrs.h | 37 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
49 unsigned Reg;
51 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
53 unsigned getSparseSetIndex() const { return Reg; }
|
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
89 unsigned Reg = MI->getOperand(1).getReg();
90 if (TargetRegisterInfo::isPhysicalRegister(Reg))
94 MachineInstr *DefMI = MRI->getVRegDef(Reg);
99 Reg = DefMI->getOperand(1).getReg();
100 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
101 DefMI = MRI->getVRegDef(Reg);
105 Reg = DefMI->getOperand(2).getReg();
106 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
107 DefMI = MRI->getVRegDef(Reg);
[all...] |
