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    Searched refs:getOpcode (Results 151 - 175 of 575) sorted by null

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  /external/llvm/lib/Target/R600/
SIInsertWaits.cpp 125 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
132 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore()));
165 if (MI.getOpcode() == AMDGPU::EXP)
216 ExpInstrTypesSeen |= MI.getOpcode() == AMDGPU::EXP ? 1 : 2;
244 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM)
AMDGPUISelDAGToDAG.cpp 112 if (Addr.getOpcode() == ISD::FrameIndex) {
120 } else if (Addr.getOpcode() == ISD::ADD) {
131 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
132 Addr.getOpcode() == ISD::TargetGlobalAddress) {
140 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
141 Addr.getOpcode() == ISD::TargetGlobalAddress) {
145 if (Addr.getOpcode() == ISD::FrameIndex) {
153 } else if (Addr.getOpcode() == ISD::ADD) {
166 unsigned int Opc = N->getOpcode();
329 if (N->getOpcode() == ISD::ConstantFP)
    [all...]
R600OptimizeVectorRegisters.cpp 63 assert (MI->getOpcode() == AMDGPU::REG_SEQUENCE);
129 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
131 switch (MI.getOpcode()) {
245 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
325 if (MI->getOpcode() != AMDGPU::REG_SEQUENCE) {
326 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
  /external/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 154 if (Op.getOpcode() == ISD::LOAD) {
163 } else if (Op.getOpcode() == ISD::STORE) {
190 switch (Op.getOpcode()) {
260 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
262 switch (Op.getOpcode()) {
286 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG)
288 else if (Node->getOpcode() == ISD::VSELECT)
290 else if (Node->getOpcode() == ISD::SELECT)
292 else if (Node->getOpcode() == ISD::UINT_TO_FP)
294 else if (Node->getOpcode() == ISD::FNEG
    [all...]
  /external/llvm/lib/Target/X86/
X86FloatingPoint.cpp 839 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
    [all...]
X86ISelDAGToDAG.cpp 303 if (N.getOpcode() != ISD::LOAD)
308 switch (U->getOpcode()) {
347 if (Op1.getOpcode() == X86ISD::Wrapper) {
349 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
368 assert(Chain.getOpcode() == ISD::TokenFactor &&
415 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
430 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
449 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
450 (N->getOpcode() == X86ISD::TC_RETURN &&
473 bool HasCallSeq = N->getOpcode() == X86ISD::CALL
    [all...]
  /dalvik/dx/src/com/android/dx/ssa/
SCCP.java 241 Rop opcode = insn.getOpcode();
274 switch (opcode.getOpcode()) {
306 switch (opcode.getOpcode()) {
367 int opcode = insn.getOpcode().getOpcode();
471 if (ropInsn.getOpcode().getBranchingness() != Rop.BRANCH_NONE
472 || ropInsn.getOpcode().isCallLike()) {
476 int opcode = insn.getOpcode().getOpcode();
  /external/dexmaker/src/dx/java/com/android/dx/ssa/
SCCP.java 242 Rop opcode = insn.getOpcode();
275 switch (opcode.getOpcode()) {
307 switch (opcode.getOpcode()) {
368 int opcode = insn.getOpcode().getOpcode();
472 if (ropInsn.getOpcode().getBranchingness() != Rop.BRANCH_NONE
473 || ropInsn.getOpcode().isCallLike()) {
477 int opcode = insn.getOpcode().getOpcode();
  /external/llvm/lib/Target/NVPTX/
NVPTXISelDAGToDAG.cpp 125 switch (N->getOpcode()) {
477 switch (N->getOpcode()) {
491 switch (N->getOpcode()) {
545 switch (N->getOpcode()) {
600 switch (N->getOpcode()) {
647 switch (N->getOpcode()) {
702 switch (N->getOpcode()) {
749 switch (N->getOpcode()) {
823 switch (N->getOpcode()) {
919 switch (N->getOpcode()) {
    [all...]
  /dalvik/dexgen/src/com/android/dexgen/dex/code/
OutputFinisher.java 369 result[i] = insns.get(i).getOpcode().getFormat();
496 Dop dop = insn.getOpcode();
545 Dop dop = insn.getOpcode();
578 Dop dop = insn.getOpcode();
598 originalFormat = insn.getOpcode().getFormat();
672 Dop dop = insn.getOpcode();
  /dalvik/dx/src/com/android/dx/dex/code/
OutputFinisher.java 379 result[i] = insns.get(i).getOpcode();
512 guess.getOpcode() != Opcodes.CONST_STRING) {
531 Dop result = findOpcodeForInsn(insn.getLowRegVersion(), insn.getOpcode());
573 Dop originalOpcode = insn.getOpcode();
608 Dop originalOpcode = insn.getOpcode();
716 Dop opcode = insn.getOpcode();
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86AsmBackend.cpp 228 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
235 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
268 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
270 if (RelaxedOp == Inst.getOpcode()) {
  /external/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 222 switch(Def->getOpcode()) {
284 if (Use->getOpcode() == ARM::t2MOVi ||
285 Use->getOpcode() == ARM::t2MOVi16)
336 unsigned Opc = MI->getOpcode();
531 unsigned Opc = MI->getOpcode();
646 if (MI->getOpcode() == ARM::t2MUL) {
828 if ((MCID.getOpcode() == ARM::t2RSBSri ||
829 MCID.getOpcode() == ARM::t2RSBri ||
830 MCID.getOpcode() == ARM::t2SXTB ||
831 MCID.getOpcode() == ARM::t2SXTH |
    [all...]
  /dalvik/dx/src/com/android/dx/ssa/back/
IdenticalBlockCombiner.java 80 || iBlock.getFirstInsn().getOpcode().getOpcode() ==
RegisterAllocator.java 116 return ndefInsn.getOpcode().getOpcode() == RegOps.MOVE_PARAM;
  /external/clang/lib/Analysis/
PseudoConstantAnalysis.cpp 103 switch (BO->getOpcode()) {
149 switch (UO->getOpcode()) {
  /external/dexmaker/src/dx/java/com/android/dx/ssa/back/
IdenticalBlockCombiner.java 85 || iBlock.getFirstInsn().getOpcode().getOpcode() ==
RegisterAllocator.java 118 return ndefInsn.getOpcode().getOpcode() == RegOps.MOVE_PARAM;
  /external/llvm/lib/Target/Hexagon/
HexagonFixupHwLoops.cpp 82 return MI->getOpcode() == Hexagon::LOOP0_r ||
83 MI->getOpcode() == Hexagon::LOOP0_i;
  /external/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 145 unsigned Opcode = MI->getOpcode();
203 unsigned Opcode = MI->getOpcode();
  /external/llvm/lib/Target/R600/MCTargetDesc/
SIMCCodeEmitter.cpp 131 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
189 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
  /external/llvm/lib/Target/SystemZ/MCTargetDesc/
SystemZMCAsmBackend.cpp 118 return getRelaxedOpcode(Inst.getOpcode()) != 0;
133 unsigned Opcode = getRelaxedOpcode(Inst.getOpcode());
  /external/llvm/lib/Transforms/InstCombine/
InstCombineAndOrXor.cpp 140 switch (Op->getOpcode()) {
349 switch (LHSI->getOpcode()) {
    [all...]
InstructionCombining.cpp 128 // The No Signed Wrap flag can be kept if the operation "B (I.getOpcode) C",
139 Instruction::BinaryOps Opcode = I.getOpcode();
202 Instruction::BinaryOps Opcode = I.getOpcode();
218 if (Op0 && Op0->getOpcode() == Opcode) {
247 if (Op1 && Op1->getOpcode() == Opcode) {
269 if (Op0 && Op0->getOpcode() == Opcode) {
289 if (Op1 && Op1->getOpcode() == Opcode) {
311 Op0->getOpcode() == Opcode && Op1->getOpcode() == Opcode &&
400 Instruction::BinaryOps TopLevelOpcode = I.getOpcode(); // o
    [all...]
  /external/smack/src/org/xbill/DNS/
Header.java 203 getOpcode() {
258 sb.append("opcode: " + Opcode.string(getOpcode()));

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1 2 3 4 5 67 8 91011>>