1 #ifndef __MSMB_ISP__ 2 #define __MSMB_ISP__ 3 4 #include <linux/videodev2.h> 5 6 #define MAX_PLANES_PER_STREAM 3 7 #define MAX_NUM_STREAM 7 8 9 #define ISP_VERSION_40 40 10 #define ISP_VERSION_32 32 11 #define ISP_NATIVE_BUF_BIT (0x10000 << 0) 12 #define ISP0_BIT (0x10000 << 1) 13 #define ISP1_BIT (0x10000 << 2) 14 #define ISP_META_CHANNEL_BIT (0x10000 << 3) 15 #define ISP_SCRATCH_BUF_BIT (0x10000 << 4) 16 #define ISP_STATS_STREAM_BIT 0x80000000 17 18 #define ISP_REG_CFG_NUM_CFG_MAX (10) 19 #define ISP_REG_CFG_CMD_LEN_MAX (3 * 1024) 20 21 enum ISP_START_PIXEL_PATTERN { 22 ISP_BAYER_RGRGRG, 23 ISP_BAYER_GRGRGR, 24 ISP_BAYER_BGBGBG, 25 ISP_BAYER_GBGBGB, 26 ISP_YUV_YCbYCr, 27 ISP_YUV_YCrYCb, 28 ISP_YUV_CbYCrY, 29 ISP_YUV_CrYCbY, 30 ISP_PIX_PATTERN_MAX 31 }; 32 33 enum msm_vfe_plane_fmt { 34 Y_PLANE, 35 CB_PLANE, 36 CR_PLANE, 37 CRCB_PLANE, 38 CBCR_PLANE, 39 VFE_PLANE_FMT_MAX 40 }; 41 42 enum msm_vfe_input_src { 43 VFE_PIX_0, 44 VFE_RAW_0, 45 VFE_RAW_1, 46 VFE_RAW_2, 47 VFE_SRC_MAX, 48 }; 49 50 enum msm_vfe_axi_stream_src { 51 PIX_ENCODER, 52 PIX_VIEWFINDER, 53 CAMIF_RAW, 54 IDEAL_RAW, 55 RDI_INTF_0, 56 RDI_INTF_1, 57 RDI_INTF_2, 58 VFE_AXI_SRC_MAX 59 }; 60 61 enum msm_vfe_frame_skip_pattern { 62 NO_SKIP, 63 EVERY_2FRAME, 64 EVERY_3FRAME, 65 EVERY_4FRAME, 66 EVERY_5FRAME, 67 EVERY_6FRAME, 68 EVERY_7FRAME, 69 EVERY_8FRAME, 70 EVERY_16FRAME, 71 EVERY_32FRAME, 72 SKIP_ALL, 73 MAX_SKIP, 74 }; 75 76 enum msm_vfe_camif_input { 77 CAMIF_DISABLED, 78 CAMIF_PAD_REG_INPUT, 79 CAMIF_MIDDI_INPUT, 80 CAMIF_MIPI_INPUT, 81 }; 82 83 struct msm_vfe_camif_cfg { 84 uint32_t lines_per_frame; 85 uint32_t pixels_per_line; 86 uint32_t first_pixel; 87 uint32_t last_pixel; 88 uint32_t first_line; 89 uint32_t last_line; 90 uint32_t epoch_line0; 91 uint32_t epoch_line1; 92 enum msm_vfe_camif_input camif_input; 93 }; 94 95 enum msm_vfe_inputmux { 96 CAMIF, 97 TESTGEN, 98 EXTERNAL_READ, 99 }; 100 101 struct msm_vfe_pix_cfg { 102 struct msm_vfe_camif_cfg camif_cfg; 103 enum msm_vfe_inputmux input_mux; 104 enum ISP_START_PIXEL_PATTERN pixel_pattern; 105 }; 106 107 struct msm_vfe_rdi_cfg { 108 uint8_t cid; 109 uint8_t frame_based; 110 }; 111 112 struct msm_vfe_input_cfg { 113 union { 114 struct msm_vfe_pix_cfg pix_cfg; 115 struct msm_vfe_rdi_cfg rdi_cfg; 116 } d; 117 enum msm_vfe_input_src input_src; 118 uint32_t input_pix_clk; 119 }; 120 121 struct msm_vfe_axi_plane_cfg { 122 uint32_t output_width; /*Include padding*/ 123 uint32_t output_height; 124 uint32_t output_stride; 125 uint32_t output_scan_lines; 126 uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/ 127 uint32_t plane_addr_offset; 128 uint8_t csid_src; /*RDI 0-2*/ 129 uint8_t rdi_cid;/*CID 1-16*/ 130 }; 131 132 struct msm_vfe_axi_stream_request_cmd { 133 uint32_t session_id; 134 uint32_t stream_id; 135 uint32_t output_format;/*Planar/RAW/Misc*/ 136 enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/ 137 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 138 139 uint32_t burst_count; 140 uint32_t hfr_mode; 141 uint8_t frame_base; 142 143 uint32_t init_frame_drop; /*MAX 31 Frames*/ 144 enum msm_vfe_frame_skip_pattern frame_skip_pattern; 145 uint8_t buf_divert; /* if TRUE no vb2 buf done. */ 146 /*Return values*/ 147 uint32_t axi_stream_handle; 148 }; 149 150 struct msm_vfe_axi_stream_release_cmd { 151 uint32_t stream_handle; 152 }; 153 154 enum msm_vfe_axi_stream_cmd { 155 STOP_STREAM, 156 START_STREAM, 157 }; 158 159 struct msm_vfe_axi_stream_cfg_cmd { 160 uint8_t num_streams; 161 uint32_t stream_handle[MAX_NUM_STREAM]; 162 enum msm_vfe_axi_stream_cmd cmd; 163 }; 164 165 enum msm_vfe_axi_stream_update_type { 166 ENABLE_STREAM_BUF_DIVERT, 167 DISABLE_STREAM_BUF_DIVERT, 168 UPDATE_STREAM_FRAMEDROP_PATTERN, 169 UPDATE_STREAM_REQUEST_FRAMES, 170 }; 171 172 struct msm_vfe_axi_stream_update_cmd { 173 uint32_t stream_handle; 174 enum msm_vfe_axi_stream_update_type update_type; 175 enum msm_vfe_frame_skip_pattern skip_pattern; 176 uint32_t request_frm_num; 177 }; 178 179 enum msm_isp_stats_type { 180 MSM_ISP_STATS_AEC, /* legacy based AEC */ 181 MSM_ISP_STATS_AF, /* legacy based AF */ 182 MSM_ISP_STATS_AWB, /* legacy based AWB */ 183 MSM_ISP_STATS_RS, /* legacy based RS */ 184 MSM_ISP_STATS_CS, /* legacy based CS */ 185 MSM_ISP_STATS_IHIST, /* legacy based HIST */ 186 MSM_ISP_STATS_SKIN, /* legacy based SKIN */ 187 MSM_ISP_STATS_BG, /* Bayer Grids */ 188 MSM_ISP_STATS_BF, /* Bayer Focus */ 189 MSM_ISP_STATS_BE, /* Bayer Exposure*/ 190 MSM_ISP_STATS_BHIST, /* Bayer Hist */ 191 MSM_ISP_STATS_MAX /* MAX */ 192 }; 193 194 struct msm_vfe_stats_stream_request_cmd { 195 uint32_t session_id; 196 uint32_t stream_id; 197 enum msm_isp_stats_type stats_type; 198 uint32_t composite_flag; 199 uint32_t framedrop_pattern; 200 uint32_t irq_subsample_pattern; 201 uint32_t buffer_offset; 202 uint32_t stream_handle; 203 }; 204 205 struct msm_vfe_stats_stream_release_cmd { 206 uint32_t stream_handle; 207 }; 208 struct msm_vfe_stats_stream_cfg_cmd { 209 uint8_t num_streams; 210 uint32_t stream_handle[MSM_ISP_STATS_MAX]; 211 uint8_t enable; 212 }; 213 214 enum msm_vfe_reg_cfg_type { 215 VFE_WRITE, 216 VFE_WRITE_MB, 217 VFE_READ, 218 VFE_CFG_MASK, 219 VFE_WRITE_DMI_16BIT, 220 VFE_WRITE_DMI_32BIT, 221 VFE_WRITE_DMI_64BIT, 222 VFE_READ_DMI_16BIT, 223 VFE_READ_DMI_32BIT, 224 VFE_READ_DMI_64BIT, 225 }; 226 227 struct msm_vfe_cfg_cmd2 { 228 uint16_t num_cfg; 229 uint16_t cmd_len; 230 void __user *cfg_data; 231 void __user *cfg_cmd; 232 }; 233 234 struct msm_vfe_reg_rw_info { 235 uint32_t reg_offset; 236 uint32_t cmd_data_offset; 237 uint32_t len; 238 }; 239 240 struct msm_vfe_reg_mask_info { 241 uint32_t reg_offset; 242 uint32_t mask; 243 uint32_t val; 244 }; 245 246 struct msm_vfe_reg_dmi_info { 247 uint32_t hi_tbl_offset; /*Optional*/ 248 uint32_t lo_tbl_offset; /*Required*/ 249 uint32_t len; 250 }; 251 252 struct msm_vfe_reg_cfg_cmd { 253 union { 254 struct msm_vfe_reg_rw_info rw_info; 255 struct msm_vfe_reg_mask_info mask_info; 256 struct msm_vfe_reg_dmi_info dmi_info; 257 } u; 258 259 enum msm_vfe_reg_cfg_type cmd_type; 260 }; 261 262 enum msm_isp_buf_type { 263 ISP_PRIVATE_BUF, 264 ISP_SHARE_BUF, 265 MAX_ISP_BUF_TYPE, 266 }; 267 268 struct msm_isp_buf_request { 269 uint32_t session_id; 270 uint32_t stream_id; 271 uint8_t num_buf; 272 uint32_t handle; 273 enum msm_isp_buf_type buf_type; 274 }; 275 276 struct msm_isp_qbuf_info { 277 uint32_t handle; 278 int buf_idx; 279 /*Only used for prepare buffer*/ 280 struct v4l2_buffer buffer; 281 /*Only used for diverted buffer*/ 282 uint32_t dirty_buf; 283 }; 284 285 struct msm_vfe_axi_src_state { 286 enum msm_vfe_input_src input_src; 287 uint32_t src_active; 288 }; 289 290 enum msm_isp_event_idx { 291 ISP_REG_UPDATE = 0, 292 ISP_START_ACK = 1, 293 ISP_STOP_ACK = 2, 294 ISP_IRQ_VIOLATION = 3, 295 ISP_WM_BUS_OVERFLOW = 4, 296 ISP_STATS_OVERFLOW = 5, 297 ISP_CAMIF_ERROR = 6, 298 ISP_SOF = 7, 299 ISP_EOF = 8, 300 ISP_FRAME_DROP = 9, 301 ISP_EVENT_MAX = 10 302 }; 303 304 #define ISP_EVENT_OFFSET 8 305 #define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) 306 #define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) 307 #define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) 308 #define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) 309 #define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) 310 #define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) 311 #define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) 312 #define ISP_EVENT_WM_BUS_OVERFLOW (ISP_EVENT_BASE + ISP_WM_BUS_OVERFLOW) 313 #define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) 314 #define ISP_EVENT_CAMIF_ERROR (ISP_EVENT_BASE + ISP_CAMIF_ERROR) 315 #define ISP_EVENT_SOF (ISP_EVENT_BASE + ISP_SOF) 316 #define ISP_EVENT_EOF (ISP_EVENT_BASE + ISP_EOF) 317 #define ISP_EVENT_FRAME_DROP (ISP_EVENT_BASE + ISP_FRAME_DROP) 318 #define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) 319 #define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) 320 #define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) 321 /* The msm_v4l2_event_data structure should match the 322 * v4l2_event.u.data field. 323 * should not exceed 64 bytes */ 324 325 struct msm_isp_buf_event { 326 uint32_t session_id; 327 uint32_t stream_id; 328 uint32_t handle; 329 int8_t buf_idx; 330 }; 331 struct msm_isp_stats_event { 332 uint32_t stats_mask; /* 4 bytes */ 333 uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */ 334 }; 335 336 struct msm_isp_stream_ack { 337 uint32_t session_id; 338 uint32_t stream_id; 339 uint32_t handle; 340 }; 341 342 struct msm_isp_event_data { 343 /*Wall clock except for buffer divert events 344 *which use monotonic clock 345 */ 346 struct timeval timestamp; 347 /* Monotonic timestamp since bootup */ 348 struct timeval mono_timestamp; 349 /* if pix is a src frame_id is from camif */ 350 uint32_t frame_id; 351 union { 352 /* START_ACK, STOP_ACK */ 353 struct msm_isp_stream_ack stream_ack; 354 /* REG_UPDATE_TRIGGER, bus over flow */ 355 enum msm_vfe_input_src input_src; 356 /* stats notify */ 357 struct msm_isp_stats_event stats; 358 /* IRQ_VIOLATION, STATS_OVER_FLOW, WM_OVER_FLOW */ 359 uint32_t irq_status_mask; 360 struct msm_isp_buf_event buf_done; 361 } u; /* union can have max 52 bytes */ 362 }; 363 364 #define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') 365 #define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') 366 #define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') 367 #define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') 368 #define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') 369 #define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') 370 #define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') 371 #define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') 372 #define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') 373 #define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') 374 #define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') 375 #define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') 376 377 #define VIDIOC_MSM_VFE_REG_CFG \ 378 _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2) 379 380 #define VIDIOC_MSM_ISP_REQUEST_BUF \ 381 _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request) 382 383 #define VIDIOC_MSM_ISP_ENQUEUE_BUF \ 384 _IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info) 385 386 #define VIDIOC_MSM_ISP_RELEASE_BUF \ 387 _IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request) 388 389 #define VIDIOC_MSM_ISP_REQUEST_STREAM \ 390 _IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd) 391 392 #define VIDIOC_MSM_ISP_CFG_STREAM \ 393 _IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd) 394 395 #define VIDIOC_MSM_ISP_RELEASE_STREAM \ 396 _IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd) 397 398 #define VIDIOC_MSM_ISP_INPUT_CFG \ 399 _IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg) 400 401 #define VIDIOC_MSM_ISP_SET_SRC_STATE \ 402 _IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state) 403 404 #define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \ 405 _IOWR('V', BASE_VIDIOC_PRIVATE+9, \ 406 struct msm_vfe_stats_stream_request_cmd) 407 408 #define VIDIOC_MSM_ISP_CFG_STATS_STREAM \ 409 _IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd) 410 411 #define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \ 412 _IOWR('V', BASE_VIDIOC_PRIVATE+11, \ 413 struct msm_vfe_stats_stream_release_cmd) 414 415 #define VIDIOC_MSM_ISP_UPDATE_STREAM \ 416 _IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd) 417 418 #define VIDIOC_MSM_ISP_CONFIG_DONE \ 419 _IOWR('V', BASE_VIDIOC_PRIVATE+14, int) 420 421 422 #endif /* __MSMB_ISP__ */ 423
