Home | History | Annotate | Download | only in SelectionDAG
      1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- c++ -*---===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef SELECTIONDAGBUILDER_H
     15 #define SELECTIONDAGBUILDER_H
     16 
     17 #include "llvm/ADT/APInt.h"
     18 #include "llvm/ADT/DenseMap.h"
     19 #include "llvm/CodeGen/SelectionDAG.h"
     20 #include "llvm/CodeGen/SelectionDAGNodes.h"
     21 #include "llvm/CodeGen/ValueTypes.h"
     22 #include "llvm/IR/Constants.h"
     23 #include "llvm/Support/CallSite.h"
     24 #include "llvm/Support/ErrorHandling.h"
     25 #include <vector>
     26 
     27 namespace llvm {
     28 
     29 class AliasAnalysis;
     30 class AllocaInst;
     31 class BasicBlock;
     32 class BitCastInst;
     33 class BranchInst;
     34 class CallInst;
     35 class DbgValueInst;
     36 class ExtractElementInst;
     37 class ExtractValueInst;
     38 class FCmpInst;
     39 class FPExtInst;
     40 class FPToSIInst;
     41 class FPToUIInst;
     42 class FPTruncInst;
     43 class Function;
     44 class FunctionLoweringInfo;
     45 class GetElementPtrInst;
     46 class GCFunctionInfo;
     47 class ICmpInst;
     48 class IntToPtrInst;
     49 class IndirectBrInst;
     50 class InvokeInst;
     51 class InsertElementInst;
     52 class InsertValueInst;
     53 class Instruction;
     54 class LoadInst;
     55 class MachineBasicBlock;
     56 class MachineInstr;
     57 class MachineRegisterInfo;
     58 class MDNode;
     59 class PHINode;
     60 class PtrToIntInst;
     61 class ReturnInst;
     62 class SDDbgValue;
     63 class SExtInst;
     64 class SelectInst;
     65 class ShuffleVectorInst;
     66 class SIToFPInst;
     67 class StoreInst;
     68 class SwitchInst;
     69 class DataLayout;
     70 class TargetLibraryInfo;
     71 class TargetLowering;
     72 class TruncInst;
     73 class UIToFPInst;
     74 class UnreachableInst;
     75 class VAArgInst;
     76 class ZExtInst;
     77 
     78 //===----------------------------------------------------------------------===//
     79 /// SelectionDAGBuilder - This is the common target-independent lowering
     80 /// implementation that is parameterized by a TargetLowering object.
     81 ///
     82 class SelectionDAGBuilder {
     83   /// CurInst - The current instruction being visited
     84   const Instruction *CurInst;
     85 
     86   DenseMap<const Value*, SDValue> NodeMap;
     87 
     88   /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
     89   /// to preserve debug information for incoming arguments.
     90   DenseMap<const Value*, SDValue> UnusedArgNodeMap;
     91 
     92   /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
     93   class DanglingDebugInfo {
     94     const DbgValueInst* DI;
     95     DebugLoc dl;
     96     unsigned SDNodeOrder;
     97   public:
     98     DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { }
     99     DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
    100       DI(di), dl(DL), SDNodeOrder(SDNO) { }
    101     const DbgValueInst* getDI() { return DI; }
    102     DebugLoc getdl() { return dl; }
    103     unsigned getSDNodeOrder() { return SDNodeOrder; }
    104   };
    105 
    106   /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
    107   /// yet seen the referent.  We defer handling these until we do see it.
    108   DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
    109 
    110 public:
    111   /// PendingLoads - Loads are not emitted to the program immediately.  We bunch
    112   /// them up and then emit token factor nodes when possible.  This allows us to
    113   /// get simple disambiguation between loads without worrying about alias
    114   /// analysis.
    115   SmallVector<SDValue, 8> PendingLoads;
    116 private:
    117 
    118   /// PendingExports - CopyToReg nodes that copy values to virtual registers
    119   /// for export to other blocks need to be emitted before any terminator
    120   /// instruction, but they have no other ordering requirements. We bunch them
    121   /// up and the emit a single tokenfactor for them just before terminator
    122   /// instructions.
    123   SmallVector<SDValue, 8> PendingExports;
    124 
    125   /// SDNodeOrder - A unique monotonically increasing number used to order the
    126   /// SDNodes we create.
    127   unsigned SDNodeOrder;
    128 
    129   /// Case - A struct to record the Value for a switch case, and the
    130   /// case's target basic block.
    131   struct Case {
    132     const Constant *Low;
    133     const Constant *High;
    134     MachineBasicBlock* BB;
    135     uint32_t ExtraWeight;
    136 
    137     Case() : Low(0), High(0), BB(0), ExtraWeight(0) { }
    138     Case(const Constant *low, const Constant *high, MachineBasicBlock *bb,
    139          uint32_t extraweight) : Low(low), High(high), BB(bb),
    140          ExtraWeight(extraweight) { }
    141 
    142     APInt size() const {
    143       const APInt &rHigh = cast<ConstantInt>(High)->getValue();
    144       const APInt &rLow  = cast<ConstantInt>(Low)->getValue();
    145       return (rHigh - rLow + 1ULL);
    146     }
    147   };
    148 
    149   struct CaseBits {
    150     uint64_t Mask;
    151     MachineBasicBlock* BB;
    152     unsigned Bits;
    153     uint32_t ExtraWeight;
    154 
    155     CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
    156              uint32_t Weight):
    157       Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
    158   };
    159 
    160   typedef std::vector<Case>           CaseVector;
    161   typedef std::vector<CaseBits>       CaseBitsVector;
    162   typedef CaseVector::iterator        CaseItr;
    163   typedef std::pair<CaseItr, CaseItr> CaseRange;
    164 
    165   /// CaseRec - A struct with ctor used in lowering switches to a binary tree
    166   /// of conditional branches.
    167   struct CaseRec {
    168     CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
    169             CaseRange r) :
    170     CaseBB(bb), LT(lt), GE(ge), Range(r) {}
    171 
    172     /// CaseBB - The MBB in which to emit the compare and branch
    173     MachineBasicBlock *CaseBB;
    174     /// LT, GE - If nonzero, we know the current case value must be less-than or
    175     /// greater-than-or-equal-to these Constants.
    176     const Constant *LT;
    177     const Constant *GE;
    178     /// Range - A pair of iterators representing the range of case values to be
    179     /// processed at this point in the binary search tree.
    180     CaseRange Range;
    181   };
    182 
    183   typedef std::vector<CaseRec> CaseRecVector;
    184 
    185   struct CaseBitsCmp {
    186     bool operator()(const CaseBits &C1, const CaseBits &C2) {
    187       return C1.Bits > C2.Bits;
    188     }
    189   };
    190 
    191   size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
    192 
    193   /// CaseBlock - This structure is used to communicate between
    194   /// SelectionDAGBuilder and SDISel for the code generation of additional basic
    195   /// blocks needed by multi-case switch statements.
    196   struct CaseBlock {
    197     CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
    198               const Value *cmpmiddle,
    199               MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
    200               MachineBasicBlock *me,
    201               uint32_t trueweight = 0, uint32_t falseweight = 0)
    202       : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
    203         TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
    204         TrueWeight(trueweight), FalseWeight(falseweight) { }
    205 
    206     // CC - the condition code to use for the case block's setcc node
    207     ISD::CondCode CC;
    208 
    209     // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
    210     // Emit by default LHS op RHS. MHS is used for range comparisons:
    211     // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
    212     const Value *CmpLHS, *CmpMHS, *CmpRHS;
    213 
    214     // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
    215     MachineBasicBlock *TrueBB, *FalseBB;
    216 
    217     // ThisBB - the block into which to emit the code for the setcc and branches
    218     MachineBasicBlock *ThisBB;
    219 
    220     // TrueWeight/FalseWeight - branch weights.
    221     uint32_t TrueWeight, FalseWeight;
    222   };
    223 
    224   struct JumpTable {
    225     JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
    226               MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
    227 
    228     /// Reg - the virtual register containing the index of the jump table entry
    229     //. to jump to.
    230     unsigned Reg;
    231     /// JTI - the JumpTableIndex for this jump table in the function.
    232     unsigned JTI;
    233     /// MBB - the MBB into which to emit the code for the indirect jump.
    234     MachineBasicBlock *MBB;
    235     /// Default - the MBB of the default bb, which is a successor of the range
    236     /// check MBB.  This is when updating PHI nodes in successors.
    237     MachineBasicBlock *Default;
    238   };
    239   struct JumpTableHeader {
    240     JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
    241                     bool E = false):
    242       First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
    243     APInt First;
    244     APInt Last;
    245     const Value *SValue;
    246     MachineBasicBlock *HeaderBB;
    247     bool Emitted;
    248   };
    249   typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
    250 
    251   struct BitTestCase {
    252     BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
    253                 uint32_t Weight):
    254       Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
    255     uint64_t Mask;
    256     MachineBasicBlock *ThisBB;
    257     MachineBasicBlock *TargetBB;
    258     uint32_t ExtraWeight;
    259   };
    260 
    261   typedef SmallVector<BitTestCase, 3> BitTestInfo;
    262 
    263   struct BitTestBlock {
    264     BitTestBlock(APInt F, APInt R, const Value* SV,
    265                  unsigned Rg, MVT RgVT, bool E,
    266                  MachineBasicBlock* P, MachineBasicBlock* D,
    267                  const BitTestInfo& C):
    268       First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
    269       Parent(P), Default(D), Cases(C) { }
    270     APInt First;
    271     APInt Range;
    272     const Value *SValue;
    273     unsigned Reg;
    274     MVT RegVT;
    275     bool Emitted;
    276     MachineBasicBlock *Parent;
    277     MachineBasicBlock *Default;
    278     BitTestInfo Cases;
    279   };
    280 
    281 private:
    282   const TargetMachine &TM;
    283 public:
    284   SelectionDAG &DAG;
    285   const DataLayout *TD;
    286   AliasAnalysis *AA;
    287   const TargetLibraryInfo *LibInfo;
    288 
    289   /// SwitchCases - Vector of CaseBlock structures used to communicate
    290   /// SwitchInst code generation information.
    291   std::vector<CaseBlock> SwitchCases;
    292   /// JTCases - Vector of JumpTable structures used to communicate
    293   /// SwitchInst code generation information.
    294   std::vector<JumpTableBlock> JTCases;
    295   /// BitTestCases - Vector of BitTestBlock structures used to communicate
    296   /// SwitchInst code generation information.
    297   std::vector<BitTestBlock> BitTestCases;
    298 
    299   // Emit PHI-node-operand constants only once even if used by multiple
    300   // PHI nodes.
    301   DenseMap<const Constant *, unsigned> ConstantsOut;
    302 
    303   /// FuncInfo - Information about the function as a whole.
    304   ///
    305   FunctionLoweringInfo &FuncInfo;
    306 
    307   /// OptLevel - What optimization level we're generating code for.
    308   ///
    309   CodeGenOpt::Level OptLevel;
    310 
    311   /// GFI - Garbage collection metadata for the function.
    312   GCFunctionInfo *GFI;
    313 
    314   /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
    315   DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
    316 
    317   /// HasTailCall - This is set to true if a call in the current
    318   /// block has been translated as a tail call. In this case,
    319   /// no subsequent DAG nodes should be created.
    320   ///
    321   bool HasTailCall;
    322 
    323   LLVMContext *Context;
    324 
    325   SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
    326                       CodeGenOpt::Level ol)
    327     : CurInst(NULL), SDNodeOrder(0), TM(dag.getTarget()),
    328       DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
    329       HasTailCall(false) {
    330   }
    331 
    332   void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
    333             const TargetLibraryInfo *li);
    334 
    335   /// clear - Clear out the current SelectionDAG and the associated
    336   /// state and prepare this SelectionDAGBuilder object to be used
    337   /// for a new block. This doesn't clear out information about
    338   /// additional blocks that are needed to complete switch lowering
    339   /// or PHI node updating; that information is cleared out as it is
    340   /// consumed.
    341   void clear();
    342 
    343   /// clearDanglingDebugInfo - Clear the dangling debug information
    344   /// map. This function is separated from the clear so that debug
    345   /// information that is dangling in a basic block can be properly
    346   /// resolved in a different basic block. This allows the
    347   /// SelectionDAG to resolve dangling debug information attached
    348   /// to PHI nodes.
    349   void clearDanglingDebugInfo();
    350 
    351   /// getRoot - Return the current virtual root of the Selection DAG,
    352   /// flushing any PendingLoad items. This must be done before emitting
    353   /// a store or any other node that may need to be ordered after any
    354   /// prior load instructions.
    355   ///
    356   SDValue getRoot();
    357 
    358   /// getControlRoot - Similar to getRoot, but instead of flushing all the
    359   /// PendingLoad items, flush all the PendingExports items. It is necessary
    360   /// to do this before emitting a terminator instruction.
    361   ///
    362   SDValue getControlRoot();
    363 
    364   SDLoc getCurSDLoc() const {
    365     return SDLoc(CurInst, SDNodeOrder);
    366   }
    367 
    368   DebugLoc getCurDebugLoc() const {
    369     return CurInst ? CurInst->getDebugLoc() : DebugLoc();
    370   }
    371 
    372   unsigned getSDNodeOrder() const { return SDNodeOrder; }
    373 
    374   void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
    375 
    376   void visit(const Instruction &I);
    377 
    378   void visit(unsigned Opcode, const User &I);
    379 
    380   // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
    381   // generate the debug data structures now that we've seen its definition.
    382   void resolveDanglingDebugInfo(const Value *V, SDValue Val);
    383   SDValue getValue(const Value *V);
    384   SDValue getNonRegisterValue(const Value *V);
    385   SDValue getValueImpl(const Value *V);
    386 
    387   void setValue(const Value *V, SDValue NewN) {
    388     SDValue &N = NodeMap[V];
    389     assert(N.getNode() == 0 && "Already set a value for this node!");
    390     N = NewN;
    391   }
    392 
    393   void setUnusedArgValue(const Value *V, SDValue NewN) {
    394     SDValue &N = UnusedArgNodeMap[V];
    395     assert(N.getNode() == 0 && "Already set a value for this node!");
    396     N = NewN;
    397   }
    398 
    399   void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
    400                             MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
    401                             MachineBasicBlock *SwitchBB, unsigned Opc);
    402   void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
    403                                     MachineBasicBlock *FBB,
    404                                     MachineBasicBlock *CurBB,
    405                                     MachineBasicBlock *SwitchBB);
    406   bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
    407   bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
    408   void CopyToExportRegsIfNeeded(const Value *V);
    409   void ExportFromCurrentBlock(const Value *V);
    410   void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
    411                    MachineBasicBlock *LandingPad = NULL);
    412 
    413   /// UpdateSplitBlock - When an MBB was split during scheduling, update the
    414   /// references that ned to refer to the last resulting block.
    415   void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
    416 
    417 private:
    418   // Terminator instructions.
    419   void visitRet(const ReturnInst &I);
    420   void visitBr(const BranchInst &I);
    421   void visitSwitch(const SwitchInst &I);
    422   void visitIndirectBr(const IndirectBrInst &I);
    423   void visitUnreachable(const UnreachableInst &I) { /* noop */ }
    424 
    425   // Helpers for visitSwitch
    426   bool handleSmallSwitchRange(CaseRec& CR,
    427                               CaseRecVector& WorkList,
    428                               const Value* SV,
    429                               MachineBasicBlock* Default,
    430                               MachineBasicBlock *SwitchBB);
    431   bool handleJTSwitchCase(CaseRec& CR,
    432                           CaseRecVector& WorkList,
    433                           const Value* SV,
    434                           MachineBasicBlock* Default,
    435                           MachineBasicBlock *SwitchBB);
    436   bool handleBTSplitSwitchCase(CaseRec& CR,
    437                                CaseRecVector& WorkList,
    438                                const Value* SV,
    439                                MachineBasicBlock* Default,
    440                                MachineBasicBlock *SwitchBB);
    441   bool handleBitTestsSwitchCase(CaseRec& CR,
    442                                 CaseRecVector& WorkList,
    443                                 const Value* SV,
    444                                 MachineBasicBlock* Default,
    445                                 MachineBasicBlock *SwitchBB);
    446 
    447   uint32_t getEdgeWeight(const MachineBasicBlock *Src,
    448                          const MachineBasicBlock *Dst) const;
    449   void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
    450                               uint32_t Weight = 0);
    451 public:
    452   void visitSwitchCase(CaseBlock &CB,
    453                        MachineBasicBlock *SwitchBB);
    454   void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
    455   void visitBitTestCase(BitTestBlock &BB,
    456                         MachineBasicBlock* NextMBB,
    457                         uint32_t BranchWeightToNext,
    458                         unsigned Reg,
    459                         BitTestCase &B,
    460                         MachineBasicBlock *SwitchBB);
    461   void visitJumpTable(JumpTable &JT);
    462   void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
    463                             MachineBasicBlock *SwitchBB);
    464 
    465 private:
    466   // These all get lowered before this pass.
    467   void visitInvoke(const InvokeInst &I);
    468   void visitResume(const ResumeInst &I);
    469 
    470   void visitBinary(const User &I, unsigned OpCode);
    471   void visitShift(const User &I, unsigned Opcode);
    472   void visitAdd(const User &I)  { visitBinary(I, ISD::ADD); }
    473   void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
    474   void visitSub(const User &I)  { visitBinary(I, ISD::SUB); }
    475   void visitFSub(const User &I);
    476   void visitMul(const User &I)  { visitBinary(I, ISD::MUL); }
    477   void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
    478   void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
    479   void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
    480   void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
    481   void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
    482   void visitSDiv(const User &I);
    483   void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
    484   void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
    485   void visitOr  (const User &I) { visitBinary(I, ISD::OR); }
    486   void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
    487   void visitShl (const User &I) { visitShift(I, ISD::SHL); }
    488   void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
    489   void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
    490   void visitICmp(const User &I);
    491   void visitFCmp(const User &I);
    492   // Visit the conversion instructions
    493   void visitTrunc(const User &I);
    494   void visitZExt(const User &I);
    495   void visitSExt(const User &I);
    496   void visitFPTrunc(const User &I);
    497   void visitFPExt(const User &I);
    498   void visitFPToUI(const User &I);
    499   void visitFPToSI(const User &I);
    500   void visitUIToFP(const User &I);
    501   void visitSIToFP(const User &I);
    502   void visitPtrToInt(const User &I);
    503   void visitIntToPtr(const User &I);
    504   void visitBitCast(const User &I);
    505 
    506   void visitExtractElement(const User &I);
    507   void visitInsertElement(const User &I);
    508   void visitShuffleVector(const User &I);
    509 
    510   void visitExtractValue(const ExtractValueInst &I);
    511   void visitInsertValue(const InsertValueInst &I);
    512   void visitLandingPad(const LandingPadInst &I);
    513 
    514   void visitGetElementPtr(const User &I);
    515   void visitSelect(const User &I);
    516 
    517   void visitAlloca(const AllocaInst &I);
    518   void visitLoad(const LoadInst &I);
    519   void visitStore(const StoreInst &I);
    520   void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
    521   void visitAtomicRMW(const AtomicRMWInst &I);
    522   void visitFence(const FenceInst &I);
    523   void visitPHI(const PHINode &I);
    524   void visitCall(const CallInst &I);
    525   bool visitMemCmpCall(const CallInst &I);
    526   bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
    527   void visitAtomicLoad(const LoadInst &I);
    528   void visitAtomicStore(const StoreInst &I);
    529 
    530   void visitInlineAsm(ImmutableCallSite CS);
    531   const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
    532   void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
    533 
    534   void visitVAStart(const CallInst &I);
    535   void visitVAArg(const VAArgInst &I);
    536   void visitVAEnd(const CallInst &I);
    537   void visitVACopy(const CallInst &I);
    538 
    539   void visitUserOp1(const Instruction &I) {
    540     llvm_unreachable("UserOp1 should not exist at instruction selection time!");
    541   }
    542   void visitUserOp2(const Instruction &I) {
    543     llvm_unreachable("UserOp2 should not exist at instruction selection time!");
    544   }
    545 
    546   void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
    547 
    548   /// EmitFuncArgumentDbgValue - If V is an function argument then create
    549   /// corresponding DBG_VALUE machine instruction for it now. At the end of
    550   /// instruction selection, they will be inserted to the entry BB.
    551   bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
    552                                 int64_t Offset, const SDValue &N);
    553 };
    554 
    555 } // end namespace llvm
    556 
    557 #endif
    558