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      1 //===-- ARMUnwindOpAsm.cpp - ARM Unwind Opcodes Assembler -------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the unwind opcode assmebler for ARM exception handling
     11 // table.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #include "ARMUnwindOpAsm.h"
     16 
     17 #include "ARMUnwindOp.h"
     18 #include "llvm/Support/ErrorHandling.h"
     19 #include "llvm/Support/LEB128.h"
     20 
     21 using namespace llvm;
     22 
     23 namespace {
     24   /// UnwindOpcodeStreamer - The simple wrapper over SmallVector to emit bytes
     25   /// with MSB to LSB per uint32_t ordering.  For example, the first byte will
     26   /// be placed in Vec[3], and the following bytes will be placed in 2, 1, 0,
     27   /// 7, 6, 5, 4, 11, 10, 9, 8, and so on.
     28   class UnwindOpcodeStreamer {
     29   private:
     30     SmallVectorImpl<uint8_t> &Vec;
     31     size_t Pos;
     32 
     33   public:
     34     UnwindOpcodeStreamer(SmallVectorImpl<uint8_t> &V) : Vec(V), Pos(3) {
     35     }
     36 
     37     /// Emit the byte in MSB to LSB per uint32_t order.
     38     inline void EmitByte(uint8_t elem) {
     39       Vec[Pos] = elem;
     40       Pos = (((Pos ^ 0x3u) + 1) ^ 0x3u);
     41     }
     42 
     43     /// Emit the size prefix.
     44     inline void EmitSize(size_t Size) {
     45       size_t SizeInWords = (Size + 3) / 4;
     46       assert(SizeInWords <= 0x100u &&
     47              "Only 256 additional words are allowed for unwind opcodes");
     48       EmitByte(static_cast<uint8_t>(SizeInWords - 1));
     49     }
     50 
     51     /// Emit the personality index prefix.
     52     inline void EmitPersonalityIndex(unsigned PI) {
     53       assert(PI < NUM_PERSONALITY_INDEX && "Invalid personality prefix");
     54       EmitByte(EHT_COMPACT | PI);
     55     }
     56 
     57     /// Fill the rest of bytes with FINISH opcode.
     58     inline void FillFinishOpcode() {
     59       while (Pos < Vec.size())
     60         EmitByte(UNWIND_OPCODE_FINISH);
     61     }
     62   };
     63 }
     64 
     65 void UnwindOpcodeAssembler::EmitRegSave(uint32_t RegSave) {
     66   if (RegSave == 0u)
     67     return;
     68 
     69   // One byte opcode to save register r14 and r11-r4
     70   if (RegSave & (1u << 4)) {
     71     // The one byte opcode will always save r4, thus we can't use the one byte
     72     // opcode when r4 is not in .save directive.
     73 
     74     // Compute the consecutive registers from r4 to r11.
     75     uint32_t Range = 0;
     76     uint32_t Mask = (1u << 4);
     77     for (uint32_t Bit = (1u << 5); Bit < (1u << 12); Bit <<= 1) {
     78       if ((RegSave & Bit) == 0u)
     79         break;
     80       ++Range;
     81       Mask |= Bit;
     82     }
     83 
     84     // Emit this opcode when the mask covers every registers.
     85     uint32_t UnmaskedReg = RegSave & 0xfff0u & (~Mask);
     86     if (UnmaskedReg == 0u) {
     87       // Pop r[4 : (4 + n)]
     88       EmitInt8(UNWIND_OPCODE_POP_REG_RANGE_R4 | Range);
     89       RegSave &= 0x000fu;
     90     } else if (UnmaskedReg == (1u << 14)) {
     91       // Pop r[14] + r[4 : (4 + n)]
     92       EmitInt8(UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range);
     93       RegSave &= 0x000fu;
     94     }
     95   }
     96 
     97   // Two bytes opcode to save register r15-r4
     98   if ((RegSave & 0xfff0u) != 0)
     99     EmitInt16(UNWIND_OPCODE_POP_REG_MASK_R4 | (RegSave >> 4));
    100 
    101   // Opcode to save register r3-r0
    102   if ((RegSave & 0x000fu) != 0)
    103     EmitInt16(UNWIND_OPCODE_POP_REG_MASK | (RegSave & 0x000fu));
    104 }
    105 
    106 /// Emit unwind opcodes for .vsave directives
    107 void UnwindOpcodeAssembler::EmitVFPRegSave(uint32_t VFPRegSave) {
    108   size_t i = 32;
    109 
    110   while (i > 16) {
    111     uint32_t Bit = 1u << (i - 1);
    112     if ((VFPRegSave & Bit) == 0u) {
    113       --i;
    114       continue;
    115     }
    116 
    117     uint32_t Range = 0;
    118 
    119     --i;
    120     Bit >>= 1;
    121 
    122     while (i > 16 && (VFPRegSave & Bit)) {
    123       --i;
    124       ++Range;
    125       Bit >>= 1;
    126     }
    127 
    128     EmitInt16(UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD_D16 |
    129               ((i - 16) << 4) | Range);
    130   }
    131 
    132   while (i > 0) {
    133     uint32_t Bit = 1u << (i - 1);
    134     if ((VFPRegSave & Bit) == 0u) {
    135       --i;
    136       continue;
    137     }
    138 
    139     uint32_t Range = 0;
    140 
    141     --i;
    142     Bit >>= 1;
    143 
    144     while (i > 0 && (VFPRegSave & Bit)) {
    145       --i;
    146       ++Range;
    147       Bit >>= 1;
    148     }
    149 
    150     EmitInt16(UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD | (i << 4) | Range);
    151   }
    152 }
    153 
    154 /// Emit unwind opcodes to copy address from source register to $sp.
    155 void UnwindOpcodeAssembler::EmitSetSP(uint16_t Reg) {
    156   EmitInt8(UNWIND_OPCODE_SET_VSP | Reg);
    157 }
    158 
    159 /// Emit unwind opcodes to add $sp with an offset.
    160 void UnwindOpcodeAssembler::EmitSPOffset(int64_t Offset) {
    161   if (Offset > 0x200) {
    162     uint8_t Buff[16];
    163     Buff[0] = UNWIND_OPCODE_INC_VSP_ULEB128;
    164     size_t ULEBSize = encodeULEB128((Offset - 0x204) >> 2, Buff + 1);
    165     EmitBytes(Buff, ULEBSize + 1);
    166   } else if (Offset > 0) {
    167     if (Offset > 0x100) {
    168       EmitInt8(UNWIND_OPCODE_INC_VSP | 0x3fu);
    169       Offset -= 0x100;
    170     }
    171     EmitInt8(UNWIND_OPCODE_INC_VSP | static_cast<uint8_t>((Offset - 4) >> 2));
    172   } else if (Offset < 0) {
    173     while (Offset < -0x100) {
    174       EmitInt8(UNWIND_OPCODE_DEC_VSP | 0x3fu);
    175       Offset += 0x100;
    176     }
    177     EmitInt8(UNWIND_OPCODE_DEC_VSP |
    178              static_cast<uint8_t>(((-Offset) - 4) >> 2));
    179   }
    180 }
    181 
    182 void UnwindOpcodeAssembler::Finalize(unsigned &PersonalityIndex,
    183                                      SmallVectorImpl<uint8_t> &Result) {
    184 
    185   UnwindOpcodeStreamer OpStreamer(Result);
    186 
    187   if (HasPersonality) {
    188     // User-specifed personality routine: [ SIZE , OP1 , OP2 , ... ]
    189     PersonalityIndex = NUM_PERSONALITY_INDEX;
    190     size_t TotalSize = Ops.size() + 1;
    191     size_t RoundUpSize = (TotalSize + 3) / 4 * 4;
    192     Result.resize(RoundUpSize);
    193     OpStreamer.EmitSize(RoundUpSize);
    194   } else {
    195     if (Ops.size() <= 3) {
    196       // __aeabi_unwind_cpp_pr0: [ 0x80 , OP1 , OP2 , OP3 ]
    197       PersonalityIndex = AEABI_UNWIND_CPP_PR0;
    198       Result.resize(4);
    199       OpStreamer.EmitPersonalityIndex(PersonalityIndex);
    200     } else {
    201       // __aeabi_unwind_cpp_pr1: [ 0x81 , SIZE , OP1 , OP2 , ... ]
    202       PersonalityIndex = AEABI_UNWIND_CPP_PR1;
    203       size_t TotalSize = Ops.size() + 2;
    204       size_t RoundUpSize = (TotalSize + 3) / 4 * 4;
    205       Result.resize(RoundUpSize);
    206       OpStreamer.EmitPersonalityIndex(PersonalityIndex);
    207       OpStreamer.EmitSize(RoundUpSize);
    208     }
    209   }
    210 
    211   // Copy the unwind opcodes
    212   for (size_t i = OpBegins.size() - 1; i > 0; --i)
    213     for (size_t j = OpBegins[i - 1], end = OpBegins[i]; j < end; ++j)
    214       OpStreamer.EmitByte(Ops[j]);
    215 
    216   // Emit the padding finish opcodes if the size is not multiple of 4.
    217   OpStreamer.FillFinishOpcode();
    218 
    219   // Reset the assembler state
    220   Reset();
    221 }
    222