1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef NVPTXISELLOWERING_H 16 #define NVPTXISELLOWERING_H 17 18 #include "NVPTX.h" 19 #include "NVPTXSubtarget.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/Target/TargetLowering.h" 22 23 namespace llvm { 24 namespace NVPTXISD { 25 enum NodeType { 26 // Start the numbering from where ISD NodeType finishes. 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 Wrapper, 29 CALL, 30 RET_FLAG, 31 LOAD_PARAM, 32 DeclareParam, 33 DeclareScalarParam, 34 DeclareRetParam, 35 DeclareRet, 36 DeclareScalarRet, 37 PrintCall, 38 PrintCallUni, 39 CallArgBegin, 40 CallArg, 41 LastCallArg, 42 CallArgEnd, 43 CallVoid, 44 CallVal, 45 CallSymbol, 46 Prototype, 47 MoveParam, 48 PseudoUseParam, 49 RETURN, 50 CallSeqBegin, 51 CallSeqEnd, 52 Dummy, 53 54 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE, 55 LoadV4, 56 LDGV2, // LDG.v2 57 LDGV4, // LDG.v4 58 LDUV2, // LDU.v2 59 LDUV4, // LDU.v4 60 StoreV2, 61 StoreV4, 62 LoadParam, 63 LoadParamV2, 64 LoadParamV4, 65 StoreParam, 66 StoreParamV2, 67 StoreParamV4, 68 StoreParamS32, // to sext and store a <32bit value, not used currently 69 StoreParamU32, // to zext and store a <32bit value, not used currently 70 StoreRetval, 71 StoreRetvalV2, 72 StoreRetvalV4 73 }; 74 } 75 76 //===--------------------------------------------------------------------===// 77 // TargetLowering Implementation 78 //===--------------------------------------------------------------------===// 79 class NVPTXTargetLowering : public TargetLowering { 80 public: 81 explicit NVPTXTargetLowering(NVPTXTargetMachine &TM); 82 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 83 84 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 85 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset, 86 SelectionDAG &DAG) const; 87 88 virtual const char *getTargetNodeName(unsigned Opcode) const; 89 90 bool isTypeSupportedInIntrinsic(MVT VT) const; 91 92 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 93 unsigned Intrinsic) const; 94 95 /// isLegalAddressingMode - Return true if the addressing mode represented 96 /// by AM is legal for this target, for a load/store of the specified type 97 /// Used to guide target specific optimizations, like loop strength 98 /// reduction (LoopStrengthReduce.cpp) and memory optimization for 99 /// address mode (CodeGenPrepare.cpp) 100 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 101 102 /// getFunctionAlignment - Return the Log2 alignment of this function. 103 virtual unsigned getFunctionAlignment(const Function *F) const; 104 105 virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const { 106 if (VT.isVector()) 107 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements()); 108 return MVT::i1; 109 } 110 111 ConstraintType getConstraintType(const std::string &Constraint) const; 112 std::pair<unsigned, const TargetRegisterClass *> 113 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; 114 115 virtual SDValue LowerFormalArguments( 116 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 117 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, 118 SmallVectorImpl<SDValue> &InVals) const; 119 120 virtual SDValue 121 LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const; 122 123 std::string getPrototype(Type *, const ArgListTy &, 124 const SmallVectorImpl<ISD::OutputArg> &, 125 unsigned retAlignment, 126 const ImmutableCallSite *CS) const; 127 128 virtual SDValue 129 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 130 const SmallVectorImpl<ISD::OutputArg> &Outs, 131 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, 132 SelectionDAG &DAG) const; 133 134 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 135 std::vector<SDValue> &Ops, 136 SelectionDAG &DAG) const; 137 138 NVPTXTargetMachine *nvTM; 139 140 // PTX always uses 32-bit shift amounts 141 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 142 143 virtual bool shouldSplitVectorElementType(EVT VT) const; 144 145 private: 146 const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here 147 148 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx, 149 EVT = MVT::i32) const; 150 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const; 151 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx); 152 153 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 154 155 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 156 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const; 157 158 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 159 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const; 160 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const; 161 162 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 163 SelectionDAG &DAG) const; 164 165 unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS, 166 Type *Ty, unsigned Idx) const; 167 }; 168 } // namespace llvm 169 170 #endif // NVPTXISELLOWERING_H 171
