| /art/compiler/dex/quick/ |
| mir_to_lir-inl.h | 66 DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & NO_OPERAND))
|
| mir_to_lir.h | 47 #define NO_OPERAND (1ULL << kNoOperand)
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| CodegenCommon.cpp | 275 assert(isPseudoOpCode(opcode) || (EncodingMap[opcode].flags & NO_OPERAND));
|
| Assemble.cpp | 103 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH,
107 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH | REG_DEF_LR,
217 kFmtUnused, -1, -1, NO_OPERAND,
397 kFmtUnused, -1, -1, NO_OPERAND,
[all...] |
| MipsLIR.h | 536 #define NO_OPERAND (1 << kNoOperand)
|
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 221 kFmtUnused, -1, -1, NO_OPERAND,
411 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH | REG_DEF_LR,
419 kFmtUnused, -1, -1, NO_OPERAND,
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | [all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| ArmLIR.h | 692 #define NO_OPERAND (1 << kNoOperand)
[all...] |
| CodegenCommon.cpp | 267 assert(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & NO_OPERAND));
|
| Assemble.cpp | 149 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH,
[all...] |
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 27 { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0 }, "int 3", "" },
211 { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },
299 { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },
[all...] |
