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  /art/compiler/dex/quick/mips/
codegen_mips.h 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
38 int r_dest, int r_dest_hi, OpSize size, int s_reg);
41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
45 int r_src, int r_src_hi, OpSize size, int s_reg);
91 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
93 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
164 LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
166 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size)
    [all...]
utility_mips.cc 337 int scale, OpSize size) {
389 int scale, OpSize size) {
435 int r_dest_hi, OpSize size, int s_reg) {
533 OpSize size, int s_reg) {
544 int r_src, int r_src_hi, OpSize size) {
626 OpSize size) {
646 int r_src, int r_src_hi, OpSize size, int s_reg) {
658 int r_dest, int r_dest_hi, OpSize size, int s_reg) {
int_mips.cc 415 void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
486 void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
  /art/compiler/dex/quick/arm/
codegen_arm.h 32 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
35 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37 int r_dest, int r_dest_hi, OpSize size, int s_reg);
40 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44 int r_src, int r_src_hi, OpSize size, int s_reg);
90 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
92 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
164 LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
166 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size)
    [all...]
utility_arm.cc 640 int scale, OpSize size) {
704 int scale, OpSize size) {
769 int r_dest_hi, OpSize size, int s_reg) {
889 OpSize size, int s_reg) {
900 int r_src, int r_src_hi, OpSize size) {
1003 OpSize size) {
1043 int displacement, int r_src, int r_src_hi, OpSize size,
1055 int displacement, int r_dest, int r_dest_hi, OpSize size,
call_arm.cc 129 OpSize size, bool long_or_double, bool is_object) {
154 OpSize size, bool long_or_double, bool is_object) {
int_arm.cc 757 void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
847 void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
    [all...]
  /art/compiler/dex/quick/x86/
codegen_x86.h 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
38 int r_dest, int r_dest_hi, OpSize size, int s_reg);
41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
45 int r_src, int r_src_hi, OpSize size, int s_reg);
91 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
93 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
utility_x86.cc 345 int displacement, int r_dest, int r_dest_hi, OpSize size,
445 int r_index, int r_dest, int scale, OpSize size) {
451 int r_dest, OpSize size, int s_reg) {
463 int displacement, int r_src, int r_src_hi, OpSize size,
544 int scale, OpSize size) {
550 int r_src, OpSize size) {
int_x86.cc 421 void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
468 void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
  /dalvik/vm/compiler/codegen/mips/
Codegen.h 81 int displacement, int rSrc, OpSize size);
Ralloc.h 36 static inline RegisterClass dvmCompilerRegClassBySize(OpSize size)
MipsLIR.h 192 typedef enum OpSize {
201 } OpSize;
  /dalvik/vm/compiler/codegen/
Ralloc.h 32 static inline RegisterClass dvmCompilerRegClassBySize(OpSize size)
222 int displacement, int rSrc, OpSize size);
  /art/compiler/dex/quick/
mir_to_lir.h 235 RegisterClass oat_reg_class_by_size(OpSize size) {
406 void GenIGet(uint32_t field_idx, int opt_flags, OpSize size,
408 void GenIPut(uint32_t field_idx, int opt_flags, OpSize size,
531 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0;
534 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0;
536 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0;
539 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0;
541 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0;
543 int r_src, int r_src_hi, OpSize size, int s_reg) = 0;
647 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array
    [all...]
gen_common.cc 623 void Mir2Lir::GenIGet(uint32_t field_idx, int opt_flags, OpSize size,
684 void Mir2Lir::GenIPut(uint32_t field_idx, int opt_flags, OpSize size,
    [all...]
  /art/compiler/dex/
compiler_enums.h 146 enum OpSize {
157 std::ostream& operator<<(std::ostream& os, const OpSize& kind);
  /dalvik/vm/compiler/codegen/arm/Thumb/
Factory.cpp 470 int rIndex, int rDest, int scale, OpSize size)
513 int rIndex, int rSrc, int scale, OpSize size)
577 OpSize size, int sReg)
698 int displacement, int rDest, OpSize size,
715 OpSize size)
808 int displacement, int rSrc, OpSize size)
  /dalvik/vm/compiler/codegen/mips/Mips32/
Factory.cpp 422 int rIndex, int rDest, int scale, OpSize size)
484 int rIndex, int rSrc, int scale, OpSize size)
594 OpSize size, int sReg)
703 int displacement, int rDest, OpSize size,
720 OpSize size)
812 int displacement, int rSrc, OpSize size)
  /dalvik/vm/compiler/codegen/arm/Thumb2/
Factory.cpp 747 int rIndex, int rDest, int scale, OpSize size)
811 int rIndex, int rSrc, int scale, OpSize size)
877 OpSize size, int sReg)
    [all...]
  /dalvik/vm/compiler/codegen/arm/
ArmLIR.h 160 typedef enum OpSize {
169 } OpSize;
    [all...]
CodegenDriver.cpp 348 static void genIGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
375 static void genIPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
405 static void genArrayGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
474 static void genArrayPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
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  /external/llvm/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h 300 // OpSize - Set if this instruction requires an operand size prefix (0x66),
303 OpSize = 1 << 6,
X86MCCodeEmitter.cpp 616 if (TSFlags & X86II::OpSize)
    [all...]
  /external/llvm/lib/Analysis/
ConstantFolding.cpp 580 unsigned OpSize = DL->getTypeSizeInBits(Op0->getType());
589 return ConstantInt::get(Op0->getType(), Offs1.zextOrTrunc(OpSize) -
590 Offs2.zextOrTrunc(OpSize));
    [all...]

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