| /art/compiler/dex/quick/ |
| local_optimizations.cc | 92 ((target_flags & (REG_DEF0 | REG_DEF1)) == (REG_DEF0 | REG_DEF1)) || // Skip wide loads.
152 if ((check_flags & (REG_DEF0 | REG_DEF1)) == (REG_DEF0 | REG_DEF1)) {
296 ((target_flags & (REG_DEF0 | REG_DEF1)) == (REG_DEF0 | REG_DEF1)) ||
|
| mir_to_lir.h | 48 #define REG_DEF0 (1ULL << kRegDef0)
77 #define REG_DEF01 (REG_DEF0 | REG_DEF1)
78 #define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
79 #define REG_DEF0_USE01 (REG_DEF0 | REG_USE01)
80 #define REG_DEF0_USE0 (REG_DEF0 | REG_USE0)
81 #define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
82 #define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
83 #define REG_DEF0_USE2 (REG_DEF0 | REG_USE2)
[all...] |
| mir_to_lir-inl.h | 168 if (flags & REG_DEF0) {
|
| /dalvik/vm/compiler/codegen/mips/ |
| MipsLIR.h | 522 #define REG_DEF0 (1 << kRegDef0)
551 #define REG_DEF01 (REG_DEF0 | REG_DEF1)
552 #define REG_DEF0_USE0 (REG_DEF0 | REG_USE0)
553 #define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
554 #define REG_DEF0_USE2 (REG_DEF0 | REG_USE2)
555 #define REG_DEF0_USE01 (REG_DEF0 | REG_USE01)
556 #define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
557 #define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
|
| CodegenCommon.cpp | 171 if (flags & REG_DEF0) {
|
| Assemble.cpp | 148 kFmtBitBlt, 15, 11, IS_QUAD_OP | REG_DEF0 | REG_USE1,
165 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
173 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
[all...] |
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 81 ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0,
87 ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0,
93 ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,
99 ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,
105 ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,
111 ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0,
117 ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0,
148 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" },
149 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" },
160 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" }
[all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| ArmLIR.h | 678 #define REG_DEF0 (1 << kRegDef0)
705 #define REG_DEF0_USE0 (REG_DEF0 | REG_USE0)
706 #define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
707 #define REG_DEF0_USE01 (REG_DEF0 | REG_USE01)
708 #define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
709 #define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
[all...] |
| Assemble.cpp | 229 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_PC
233 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_SP
282 IS_BINARY_OP | REG_DEF0 | SETS_CCODES,
344 IS_BINARY_OP | REG_DEF0 | REG_USE0 | REG_USE_LIST1 | IS_STORE,
484 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
488 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
568 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
[all...] |
| CodegenCommon.cpp | 153 if (flags & REG_DEF0) {
|
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 228 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_PC
232 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_SP
281 IS_BINARY_OP | REG_DEF0 | SETS_CCODES,
343 IS_BINARY_OP | REG_DEF0 | REG_USE0 | REG_USE_LIST1 | IS_STORE,
484 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
488 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
568 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
[all...] |
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 152 kFmtBitBlt, 15, 11, IS_QUAD_OP | REG_DEF0 | REG_USE1,
169 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
177 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
399 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | REG_USE_LR |
403 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | NEEDS_FIXUP,
[all...] |
