| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 101 IS_TERTIARY_OP | REG_DEF0_USE12 | SETS_CCODES,
224 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
240 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
248 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
252 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
256 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
386 IS_TERTIARY_OP | REG_DEF0_USE12 | SETS_CCODES,
412 IS_TERTIARY_OP | REG_DEF0_USE12,
416 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
428 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
[all...] |
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 95 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
99 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
213 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
217 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
225 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
229 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
263 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
267 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
275 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
283 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
[all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| Assemble.cpp | 102 IS_TERTIARY_OP | REG_DEF0_USE12 | SETS_CCODES,
225 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
241 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
249 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
253 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
257 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
387 IS_TERTIARY_OP | REG_DEF0_USE12 | SETS_CCODES,
412 IS_TERTIARY_OP | REG_DEF0_USE12,
416 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
428 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
[all...] |
| ArmLIR.h | 708 #define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Assemble.cpp | 91 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
95 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
209 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
213 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
221 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
225 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
259 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
263 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
271 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
279 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
[all...] |
| MipsLIR.h | 556 #define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
|
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 133 { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
137 { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
140 { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
147 { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },
159 { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },
171 { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },
178 { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 81 #define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
[all...] |
