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      1 //===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the RegisterClassInfo class which provides dynamic
     11 // information about target register classes. Callee saved and reserved
     12 // registers depends on calling conventions and other dynamic information, so
     13 // some things cannot be determined statically.
     14 //
     15 //===----------------------------------------------------------------------===//
     16 
     17 #define DEBUG_TYPE "regalloc"
     18 #include "llvm/CodeGen/RegisterClassInfo.h"
     19 #include "llvm/CodeGen/MachineFunction.h"
     20 #include "llvm/CodeGen/MachineRegisterInfo.h"
     21 #include "llvm/Support/CommandLine.h"
     22 #include "llvm/Support/Debug.h"
     23 #include "llvm/Support/raw_ostream.h"
     24 #include "llvm/Target/TargetMachine.h"
     25 
     26 using namespace llvm;
     27 
     28 static cl::opt<unsigned>
     29 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
     30          cl::desc("Limit all regclasses to N registers"));
     31 
     32 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
     33 {}
     34 
     35 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
     36   bool Update = false;
     37   MF = &mf;
     38 
     39   // Allocate new array the first time we see a new target.
     40   if (MF->getTarget().getRegisterInfo() != TRI) {
     41     TRI = MF->getTarget().getRegisterInfo();
     42     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
     43     unsigned NumPSets = TRI->getNumRegPressureSets();
     44     PSetLimits.reset(new unsigned[NumPSets]);
     45     std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
     46     Update = true;
     47   }
     48 
     49   // Does this MF have different CSRs?
     50   const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
     51   if (Update || CSR != CalleeSaved) {
     52     // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
     53     // overlapping CSR.
     54     CSRNum.clear();
     55     CSRNum.resize(TRI->getNumRegs(), 0);
     56     for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
     57       for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
     58         CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
     59     Update = true;
     60   }
     61   CalleeSaved = CSR;
     62 
     63   // Different reserved registers?
     64   const BitVector &RR = MF->getRegInfo().getReservedRegs();
     65   if (Reserved.size() != RR.size() || RR != Reserved) {
     66     Update = true;
     67     Reserved = RR;
     68   }
     69 
     70   // Invalidate cached information from previous function.
     71   if (Update)
     72     ++Tag;
     73 }
     74 
     75 /// compute - Compute the preferred allocation order for RC with reserved
     76 /// registers filtered out. Volatile registers come first followed by CSR
     77 /// aliases ordered according to the CSR order specified by the target.
     78 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
     79   RCInfo &RCI = RegClass[RC->getID()];
     80 
     81   // Raw register count, including all reserved regs.
     82   unsigned NumRegs = RC->getNumRegs();
     83 
     84   if (!RCI.Order)
     85     RCI.Order.reset(new MCPhysReg[NumRegs]);
     86 
     87   unsigned N = 0;
     88   SmallVector<MCPhysReg, 16> CSRAlias;
     89   unsigned MinCost = 0xff;
     90   unsigned LastCost = ~0u;
     91   unsigned LastCostChange = 0;
     92 
     93   // FIXME: Once targets reserve registers instead of removing them from the
     94   // allocation order, we can simply use begin/end here.
     95   ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
     96   for (unsigned i = 0; i != RawOrder.size(); ++i) {
     97     unsigned PhysReg = RawOrder[i];
     98     // Remove reserved registers from the allocation order.
     99     if (Reserved.test(PhysReg))
    100       continue;
    101     unsigned Cost = TRI->getCostPerUse(PhysReg);
    102     MinCost = std::min(MinCost, Cost);
    103 
    104     if (CSRNum[PhysReg])
    105       // PhysReg aliases a CSR, save it for later.
    106       CSRAlias.push_back(PhysReg);
    107     else {
    108       if (Cost != LastCost)
    109         LastCostChange = N;
    110       RCI.Order[N++] = PhysReg;
    111       LastCost = Cost;
    112     }
    113   }
    114   RCI.NumRegs = N + CSRAlias.size();
    115   assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
    116 
    117   // CSR aliases go after the volatile registers, preserve the target's order.
    118   for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
    119     unsigned PhysReg = CSRAlias[i];
    120     unsigned Cost = TRI->getCostPerUse(PhysReg);
    121     if (Cost != LastCost)
    122       LastCostChange = N;
    123     RCI.Order[N++] = PhysReg;
    124     LastCost = Cost;
    125   }
    126 
    127   // Register allocator stress test.  Clip register class to N registers.
    128   if (StressRA && RCI.NumRegs > StressRA)
    129     RCI.NumRegs = StressRA;
    130 
    131   // Check if RC is a proper sub-class.
    132   if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
    133     if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
    134       RCI.ProperSubClass = true;
    135 
    136   RCI.MinCost = uint8_t(MinCost);
    137   RCI.LastCostChange = LastCostChange;
    138 
    139   DEBUG({
    140     dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
    141     for (unsigned I = 0; I != RCI.NumRegs; ++I)
    142       dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
    143     dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
    144   });
    145 
    146   // RCI is now up-to-date.
    147   RCI.Tag = Tag;
    148 }
    149 
    150 /// This is not accurate because two overlapping register sets may have some
    151 /// nonoverlapping reserved registers. However, computing the allocation order
    152 /// for all register classes would be too expensive.
    153 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
    154   const TargetRegisterClass *RC = 0;
    155   unsigned NumRCUnits = 0;
    156   for (TargetRegisterInfo::regclass_iterator
    157          RI = TRI->regclass_begin(), RE = TRI->regclass_end(); RI != RE; ++RI) {
    158     const int *PSetID = TRI->getRegClassPressureSets(*RI);
    159     for (; *PSetID != -1; ++PSetID) {
    160       if ((unsigned)*PSetID == Idx)
    161         break;
    162     }
    163     if (*PSetID == -1)
    164       continue;
    165 
    166     // Found a register class that counts against this pressure set.
    167     // For efficiency, only compute the set order for the largest set.
    168     unsigned NUnits = TRI->getRegClassWeight(*RI).WeightLimit;
    169     if (!RC || NUnits > NumRCUnits) {
    170       RC = *RI;
    171       NumRCUnits = NUnits;
    172     }
    173   }
    174   compute(RC);
    175   unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
    176   return TRI->getRegPressureSetLimit(Idx)
    177     - TRI->getRegClassWeight(RC).RegWeight * NReserved;
    178 }
    179