1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Parent TargetRegisterInfo class common to all hw codegen targets. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "AMDGPURegisterInfo.h" 16 #include "AMDGPUTargetMachine.h" 17 18 using namespace llvm; 19 20 AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm) 21 : AMDGPUGenRegisterInfo(0), 22 TM(tm) 23 { } 24 25 //===----------------------------------------------------------------------===// 26 // Function handling callbacks - Functions are a seldom used feature of GPUS, so 27 // they are not supported at this time. 28 //===----------------------------------------------------------------------===// 29 30 const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister; 31 32 const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) 33 const { 34 return &CalleeSavedReg; 35 } 36 37 void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, 38 int SPAdj, 39 unsigned FIOperandNum, 40 RegScavenger *RS) const { 41 assert(!"Subroutines not supported yet"); 42 } 43 44 unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const { 45 assert(!"Subroutines not supported yet"); 46 return 0; 47 } 48 49 unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const { 50 51 switch(IndirectIndex) { 52 case 0: return AMDGPU::sub0; 53 case 1: return AMDGPU::sub1; 54 case 2: return AMDGPU::sub2; 55 case 3: return AMDGPU::sub3; 56 case 4: return AMDGPU::sub4; 57 case 5: return AMDGPU::sub5; 58 case 6: return AMDGPU::sub6; 59 case 7: return AMDGPU::sub7; 60 case 8: return AMDGPU::sub8; 61 case 9: return AMDGPU::sub9; 62 case 10: return AMDGPU::sub10; 63 case 11: return AMDGPU::sub11; 64 case 12: return AMDGPU::sub12; 65 case 13: return AMDGPU::sub13; 66 case 14: return AMDGPU::sub14; 67 case 15: return AMDGPU::sub15; 68 default: llvm_unreachable("indirect index out of range"); 69 } 70 } 71 72 #define GET_REGINFO_TARGET_DESC 73 #include "AMDGPUGenRegisterInfo.inc" 74
