| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 73 unsigned Reg, unsigned Lane,
79 unsigned DReg, unsigned Lane,
94 DebugLoc DL, unsigned DReg, unsigned Lane,
434 unsigned Reg, unsigned Lane, bool QPR) {
443 .addImm(Lane));
448 // Creates a SPR register from a DPR by copying the value in lane 0.
453 unsigned DReg, unsigned Lane,
460 .addReg(DReg, 0, Lane);
504 DebugLoc DL, unsigned DReg, unsigned Lane,
513 .addImm(Lane);
[all...] |
| ARMExpandPseudoInsts.cpp | 89 // For quad-register load-lane and store-lane pseudo instructors, the
91 // OddDblSpc depending on the lane number operand.
108 uint8_t RegElts; // elements per D register; used for lane ops
503 // The lane operand is always the 3rd from last operand, before the 2
505 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
507 // Adjust the lane and spacing as needed for Q registers.
508 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
509 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
511 Lane -= RegElts
[all...] |
| ARMISelDAGToDAG.cpp | 221 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
[all...] |
| ARMBaseInstrInfo.cpp | 63 bool HasLane; // True if instruction has an extra "lane" operand.
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 940 unsigned Writemask = 0, Lane = 0;
[all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | 376 Scalar(S), User(U), Lane(L){};
381 // Which lane does the scalar belong to.
382 int Lane;
422 // For each lane:
423 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) {
424 Value *Scalar = Entry->Scalars[Lane];
448 DEBUG(dbgs() << "SLP: Need to extract:" << **User << " from lane " <<
449 Lane << " from " << *Scalar << ".\n")
[all...] |
