| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
45 MachineInstr *DefMI = LastMI;
61 DefMI = &*I;
65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
67 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
|
| MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg);
96 if (DefMI->getParent() != MBB)
98 if (DefMI->isCopyLike()) {
99 Reg = DefMI->getOperand(1).getReg();
101 DefMI = MRI->getVRegDef(Reg);
104 } else if (DefMI->isInsertSubreg()) {
105 Reg = DefMI->getOperand(2).getReg();
107 DefMI = MRI->getVRegDef(Reg);
113 return DefMI;
148 MachineInstr *DefMI = MRI->getVRegDef(Reg)
[all...] |
| ARMBaseInstrInfo.h | 215 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
223 const MachineInstr *DefMI, unsigned DefIdx,
276 const MachineInstr *DefMI, unsigned DefIdx,
279 const MachineInstr *DefMI, unsigned DefIdx) const;
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 156 const MachineInstr *DefMI, unsigned DefOperIdx,
160 return TII->defaultDefLatency(&SchedModel, DefMI);
165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
169 unsigned DefClass = DefMI->getDesc().getSchedClass();
176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
184 TII->defaultDefLatency(&SchedModel, DefMI));
188 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
212 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
213 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef())
[all...] |
| LiveRangeEdit.cpp | 45 const MachineInstr *DefMI,
47 assert(DefMI && "Missing instruction");
49 if (!TII.isTriviallyReMaterializable(DefMI, aa))
61 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def);
62 if (!DefMI)
64 checkRematerializable(VNI, DefMI, aa);
161 MachineInstr *DefMI = 0, *UseMI = 0;
169 if (DefMI && DefMI != MI)
173 DefMI = MI
[all...] |
| TargetInstrInfo.cpp | 623 const MachineInstr *DefMI) const {
624 if (DefMI->isTransient())
626 if (DefMI->mayLoad())
628 if (isHighLatencyDef(DefMI->getOpcode()))
646 const MachineInstr *DefMI,
651 unsigned DefClass = DefMI->getDesc().getSchedClass();
656 /// Both DefMI and UseMI must be valid. By default, call directly to the
660 const MachineInstr *DefMI, unsigned DefIdx,
662 unsigned DefClass = DefMI->getDesc().getSchedClass();
671 const MachineInstr *DefMI) const
[all...] |
| PeepholeOptimizer.cpp | 338 MachineInstr *DefMI = MRI->getVRegDef(Src);
339 if (!DefMI || !DefMI->isBitcast())
343 NumDefs = DefMI->getDesc().getNumDefs();
344 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs;
348 const MachineOperand &MO = DefMI->getOperand(i);
554 MachineInstr *DefMI = 0;
556 FoldAsLoadDefReg, DefMI);
558 // Update LocalMIs since we replaced MI with FoldMI and deleted DefMI.
562 LocalMIs.erase(DefMI);
[all...] |
| RegisterCoalescer.cpp | 593 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
594 if (!DefMI)
596 if (!DefMI->isCommutable())
598 // If DefMI is a two-address instruction then commuting it will change the
600 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
603 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
606 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
615 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
641 << *DefMI);
645 MachineBasicBlock *MBB = DefMI->getParent()
[all...] |
| MachineTraceMetrics.cpp | 617 const MachineInstr *DefMI;
621 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp)
622 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {}
630 DefMI = &*DefI;
770 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
772 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()];
775 unsigned Len = LIR.Height + Cycles[DefMI].Depth;
847 BlockInfo[Dep.DefMI->getParent()->getNumber()];
852 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth
[all...] |
| InlineSpiller.cpp | 112 MachineInstr *DefMI;
123 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
126 bool hasDef() const { return DefByOrigPHI || DefMI; }
334 if (SVI.DefMI)
335 OS << " def: " << *SVI.DefMI;
398 DepSV.DefMI = SV.DefMI;
486 return SVI->second.DefMI;
604 SVI->second.DefMI = MI;
625 return SVI->second.DefMI;
[all...] |
| MachineCSE.cpp | 128 MachineInstr *DefMI = MRI->getVRegDef(Reg);
129 if (!DefMI->isCopy())
131 unsigned SrcReg = DefMI->getOperand(1).getReg();
134 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
138 DEBUG(dbgs() << "Coalescing: " << *DefMI);
142 DefMI->eraseFromParent();
|
| PHIElimination.cpp | 154 MachineInstr *DefMI = *I;
155 unsigned DefReg = DefMI->getOperand(0).getReg();
158 LIS->RemoveMachineInstrFromMaps(DefMI);
159 DefMI->eraseFromParent();
392 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
393 if (DefMI->isImplicitDef())
394 ImpDefs.insert(DefMI);
|
| EarlyIfConversion.cpp | 244 MachineInstr *DefMI = MRI->getVRegDef(Reg);
245 if (!DefMI || DefMI->getParent() != Head)
247 if (InsertAfter.insert(DefMI))
248 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
249 if (DefMI->isTerminator()) {
|
| MachineSink.cpp | 140 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
141 if (DefMI->isCopyLike())
143 DEBUG(dbgs() << "Coalescing: " << *DefMI);
|
| TwoAddressInstructionPass.cpp | 407 MachineInstr *DefMI = &MI;
413 if (!isPlainlyKilled(DefMI, Reg, LIS))
422 DefMI = &*Begin;
427 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| StrongPHIElimination.cpp | 253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
254 if (DefMI)
255 PHISrcDefs[DefMI->getParent()].push_back(DefMI);
|
| TailDuplication.cpp | 236 MachineInstr *DefMI = MRI->getVRegDef(VReg);
238 if (DefMI) {
239 DefBB = DefMI->getParent();
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 145 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
160 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
|
| LiveRangeEdit.h | 156 /// values if DefMI may be rematerializable.
157 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
|
| MachineTraceMetrics.h | 307 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 154 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
|
| PPCInstrInfo.cpp | 810 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
814 unsigned DefOpc = DefMI->getOpcode();
817 if (!DefMI->getOperand(1).isImm())
819 if (DefMI->getOperand(1).getImm() != 0)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 385 const MachineInstr *DefMI, unsigned DefIdx,
407 /// defined by the load we are trying to fold. DefMI returns the machine
413 MachineInstr *&DefMI) const;
|
