| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 225 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
230 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
235 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
259 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
264 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
269 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
280 { ISD::SDIV, MVT::v8i16, 8*20 },
284 { ISD::UDIV, MVT::v8i16, 8*20 },
372 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| X86FastISel.cpp | 279 case MVT::v8i16:
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 225 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
226 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
250 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
251 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
279 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
280 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
461 { ISD::VECTOR_SHUFFLE, MVT::v8i16, 2 },
513 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
514 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
515 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMISelLowering.cpp | 466 addQRTypeForNEON(MVT::v8i16);
545 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
583 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 79 v8i16 = 28, // 8 x i16 enumerator in enum:llvm::MVT::SimpleValueType
211 return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 ||
277 case v8i16:
318 case v8i16:
390 case v8i16:
504 if (NumElements == 8) return MVT::v8i16;
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 110 DecodePSHUFHWMask(MVT::v8i16,
130 DecodePSHUFLWMask(MVT::v8i16,
170 DecodeUNPCKHMask(MVT::v8i16, ShuffleMask);
243 DecodeUNPCKLMask(MVT::v8i16, ShuffleMask);
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 146 case MVT::v8i16: return "v8i16";
209 case MVT::v8i16: return VectorType::get(Type::getInt16Ty(Context), 8);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 631 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
640 else if (VecVT == MVT::v8i16)
654 else if (VecVT == MVT::v8i16)
667 else if (VecVT == MVT::v8i16)
694 // types (v16i8, v8i16, v4i32, and v4f32).
699 case MVT::v8i16:
[all...] |
| PPCISelLowering.cpp | 465 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
477 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
484 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 87 case MVT::v8i16: return "MVT::v8i16";
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 66 addRegisterClass(MVT::v8i16, &AArch64::VPR128RegClass);
276 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
288 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
[all...] |
