| /external/oprofile/events/mips/25K/ |
| events | 6 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : CPU cycles
|
| /external/oprofile/events/mips/r12000/ |
| events | 4 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : Cycles
|
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/test/ |
| test_abc.py | 141 self.assertRaises(RuntimeError, A1.register, A) # cycles not allowed
149 self.assertRaises(RuntimeError, C.register, A) # cycles not allowed
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/test/ |
| test_abc.py | 141 self.assertRaises(RuntimeError, A1.register, A) # cycles not allowed
149 self.assertRaises(RuntimeError, C.register, A) # cycles not allowed
|
| /libcore/luni/src/main/java/java/util/concurrent/ |
| ArrayBlockingQueue.java | 745 * (1) keeping track of the number of "cycles", that is, the
799 int cycles = 0; field in class:ArrayBlockingQueue.Itrs
890 cycles++;
1092 final int cycles = itrs.cycles; local
1280 final int cycles = itrs.cycles; local
[all...] |
| /external/chromium_org/third_party/openssl/openssl/crypto/sha/asm/ |
| sha1-armv4-large.pl | 16 # impl size in bytes comp cycles[*] measured performance
42 # ~990 cycles.
47 # Cortex A8 core and in absolute terms ~870 cycles per input block
48 # [or 13.6 cycles per byte].
53 # improvement on Cortex A8 core and 12.2 cycles per byte.
|
| sha1-sparcv9a.pl | 31 # (*) "Pipe-lined" means that even if it takes several cycles to
107 # cycles for given instruction assuming 1 cycle latency for simple VIS
108 # instructions, such as on UltraSPARC-I&II, 3 cycles latency, such as
109 # on UltraSPARC-III&IV, and 2 cycles latency(*), respectively. Being
118 # ~9.3 cycles per SHA1 round. Timings mentioned above are theoretical
119 # lower limits. Real-life performance was measured to be 6.6 cycles
122 # which "push down" average theoretical timing to 8 cycles...
124 # (*) SPARC64-V[II] was originally believed to have 2 cycles VIS
136 # scheduled for latency of 2 cycles, because there are not enough IALU
|
| /external/openssl/crypto/sha/asm/ |
| sha1-armv4-large.pl | 16 # impl size in bytes comp cycles[*] measured performance
42 # ~990 cycles.
47 # Cortex A8 core and in absolute terms ~870 cycles per input block
48 # [or 13.6 cycles per byte].
53 # improvement on Cortex A8 core and 12.2 cycles per byte.
|
| sha1-sparcv9a.pl | 31 # (*) "Pipe-lined" means that even if it takes several cycles to
107 # cycles for given instruction assuming 1 cycle latency for simple VIS
108 # instructions, such as on UltraSPARC-I&II, 3 cycles latency, such as
109 # on UltraSPARC-III&IV, and 2 cycles latency(*), respectively. Being
118 # ~9.3 cycles per SHA1 round. Timings mentioned above are theoretical
119 # lower limits. Real-life performance was measured to be 6.6 cycles
122 # which "push down" average theoretical timing to 8 cycles...
124 # (*) SPARC64-V[II] was originally believed to have 2 cycles VIS
136 # scheduled for latency of 2 cycles, because there are not enough IALU
|
| /external/oprofile/events/x86-64/hammer/ |
| events | 23 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired
30 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
58 event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
89 event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
90 event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
|
| /external/chromium_org/third_party/openssl/openssl/crypto/modes/asm/ |
| ghash-x86.pl | 19 # are for streamed GHASH subroutine and are expressed in cycles per
43 # 11-13 cycles on contemporary x86 cores. As for choice of MMX in
48 # Add PCLMULQDQ version performing at 2.10 cycles per processed byte.
50 # instruction latency appears to be 14 cycles and there can't be more
52 # Karatsuba multiplication would take 28 cycles *plus* few cycles for
64 # cycles and Naggr chosen by Intel is 4, resulting in 2.05 cycles per
67 # which for a single multiplication is ~5 cycles. Unfortunately Intel
70 # alone resulted in 2.46 cycles per byte of out 16KB buffer. Note tha
[all...] |
| /external/openssl/crypto/modes/asm/ |
| ghash-x86.pl | 19 # are for streamed GHASH subroutine and are expressed in cycles per
43 # 11-13 cycles on contemporary x86 cores. As for choice of MMX in
48 # Add PCLMULQDQ version performing at 2.10 cycles per processed byte.
50 # instruction latency appears to be 14 cycles and there can't be more
52 # Karatsuba multiplication would take 28 cycles *plus* few cycles for
64 # cycles and Naggr chosen by Intel is 4, resulting in 2.05 cycles per
67 # which for a single multiplication is ~5 cycles. Unfortunately Intel
70 # alone resulted in 2.46 cycles per byte of out 16KB buffer. Note tha
[all...] |
| /external/aac/libFDK/src/arm/ |
| dct_arm.cpp | 91 With this version, we save 2 cycles per loop iteration.
114 /* 44 cycles for 2 iterations = 22 cycles/iteration */
206 /* 42 cycles for 2 iterations = 21 cycles/iteration */
379 /* 50 cycles for 2 iterations = 25 cycles/iteration */
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCSchedule440.td | 77 // 33 cycles (multiply also calculates its result in IWB). For all
82 // The L1 cache hit latency is four cycles for floating point loads
83 // and three cycles for integer loads.
96 // have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
97 // update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
98 // loads take 4 cycles (for L1 hit).
[all...] |
| /external/linux-tools-perf/ |
| builtin-stat.c | 19 5,205,202,243 cycles # 3.046 GHz
20 3,856,436,920 stalled-cycles-frontend # 74.09% frontend cycles idle
21 1,600,790,871 stalled-cycles-backend # 30.75% backend cycles idle
23 # 1.48 stalled cycles per insn
577 fprintf(stderr, " frontend cycles idle ");
600 fprintf(stderr, " backend cycles idle ");
789 fprintf(stderr, "\n # %5.2f stalled cycles per insn", ratio);
[all...] |
| /prebuilts/gcc/darwin-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/gcov-src/ |
| gcov-io.h | 62 increments fast enough and cycles slow enough to distinguish
63 different compile/run/compile cycles.
626 gcov_unsigned_t lt_10; /* per 10k with latency <= 10 cycles */
627 gcov_unsigned_t lt_32; /* per 10k with latency <= 32 cycles */
628 gcov_unsigned_t lt_64; /* per 10k with latency <= 64 cycles */
629 gcov_unsigned_t lt_256; /* per 10k with latency <= 256 cycles */
630 gcov_unsigned_t lt_1024; /* per 10k with latency <= 1024 cycles */
631 gcov_unsigned_t gt_1024; /* per 10k with latency > 1024 cycles */
632 gcov_unsigned_t wself; /* weighted average cost of this miss in cycles */
[all...] |
| /prebuilts/gcc/darwin-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/gcov-src/ |
| gcov-io.h | 62 increments fast enough and cycles slow enough to distinguish
63 different compile/run/compile cycles.
626 gcov_unsigned_t lt_10; /* per 10k with latency <= 10 cycles */
627 gcov_unsigned_t lt_32; /* per 10k with latency <= 32 cycles */
628 gcov_unsigned_t lt_64; /* per 10k with latency <= 64 cycles */
629 gcov_unsigned_t lt_256; /* per 10k with latency <= 256 cycles */
630 gcov_unsigned_t lt_1024; /* per 10k with latency <= 1024 cycles */
631 gcov_unsigned_t gt_1024; /* per 10k with latency > 1024 cycles */
632 gcov_unsigned_t wself; /* weighted average cost of this miss in cycles */
[all...] |
| /prebuilts/gcc/darwin-x86/mips/mipsel-linux-android-4.6/lib/gcc/mipsel-linux-android/4.6/gcov-src/ |
| gcov-io.h | 62 increments fast enough and cycles slow enough to distinguish
63 different compile/run/compile cycles.
626 gcov_unsigned_t lt_10; /* per 10k with latency <= 10 cycles */
627 gcov_unsigned_t lt_32; /* per 10k with latency <= 32 cycles */
628 gcov_unsigned_t lt_64; /* per 10k with latency <= 64 cycles */
629 gcov_unsigned_t lt_256; /* per 10k with latency <= 256 cycles */
630 gcov_unsigned_t lt_1024; /* per 10k with latency <= 1024 cycles */
631 gcov_unsigned_t gt_1024; /* per 10k with latency > 1024 cycles */
632 gcov_unsigned_t wself; /* weighted average cost of this miss in cycles */
[all...] |
| /prebuilts/gcc/darwin-x86/x86/i686-linux-android-4.6/lib/gcc/i686-linux-android/4.6/gcov-src/ |
| gcov-io.h | 62 increments fast enough and cycles slow enough to distinguish
63 different compile/run/compile cycles.
626 gcov_unsigned_t lt_10; /* per 10k with latency <= 10 cycles */
627 gcov_unsigned_t lt_32; /* per 10k with latency <= 32 cycles */
628 gcov_unsigned_t lt_64; /* per 10k with latency <= 64 cycles */
629 gcov_unsigned_t lt_256; /* per 10k with latency <= 256 cycles */
630 gcov_unsigned_t lt_1024; /* per 10k with latency <= 1024 cycles */
631 gcov_unsigned_t gt_1024; /* per 10k with latency > 1024 cycles */
632 gcov_unsigned_t wself; /* weighted average cost of this miss in cycles */
[all...] |
| /prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/gcov-src/ |
| gcov-io.h | 62 increments fast enough and cycles slow enough to distinguish
63 different compile/run/compile cycles.
626 gcov_unsigned_t lt_10; /* per 10k with latency <= 10 cycles */
627 gcov_unsigned_t lt_32; /* per 10k with latency <= 32 cycles */
628 gcov_unsigned_t lt_64; /* per 10k with latency <= 64 cycles */
629 gcov_unsigned_t lt_256; /* per 10k with latency <= 256 cycles */
630 gcov_unsigned_t lt_1024; /* per 10k with latency <= 1024 cycles */
631 gcov_unsigned_t gt_1024; /* per 10k with latency > 1024 cycles */
632 gcov_unsigned_t wself; /* weighted average cost of this miss in cycles */
[all...] |
| /prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/gcov-src/ |
| gcov-io.h | 62 increments fast enough and cycles slow enough to distinguish
63 different compile/run/compile cycles.
626 gcov_unsigned_t lt_10; /* per 10k with latency <= 10 cycles */
627 gcov_unsigned_t lt_32; /* per 10k with latency <= 32 cycles */
628 gcov_unsigned_t lt_64; /* per 10k with latency <= 64 cycles */
629 gcov_unsigned_t lt_256; /* per 10k with latency <= 256 cycles */
630 gcov_unsigned_t lt_1024; /* per 10k with latency <= 1024 cycles */
631 gcov_unsigned_t gt_1024; /* per 10k with latency > 1024 cycles */
632 gcov_unsigned_t wself; /* weighted average cost of this miss in cycles */
[all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/lib/gcc/i686-linux/4.6.x-google/gcov-src/ |
| gcov-io.h | 62 increments fast enough and cycles slow enough to distinguish
63 different compile/run/compile cycles.
626 gcov_unsigned_t lt_10; /* per 10k with latency <= 10 cycles */
627 gcov_unsigned_t lt_32; /* per 10k with latency <= 32 cycles */
628 gcov_unsigned_t lt_64; /* per 10k with latency <= 64 cycles */
629 gcov_unsigned_t lt_256; /* per 10k with latency <= 256 cycles */
630 gcov_unsigned_t lt_1024; /* per 10k with latency <= 1024 cycles */
631 gcov_unsigned_t gt_1024; /* per 10k with latency > 1024 cycles */
632 gcov_unsigned_t wself; /* weighted average cost of this miss in cycles */
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/lib/gcc/x86_64-linux/4.6.x-google/gcov-src/ |
| gcov-io.h | 62 increments fast enough and cycles slow enough to distinguish
63 different compile/run/compile cycles.
626 gcov_unsigned_t lt_10; /* per 10k with latency <= 10 cycles */
627 gcov_unsigned_t lt_32; /* per 10k with latency <= 32 cycles */
628 gcov_unsigned_t lt_64; /* per 10k with latency <= 64 cycles */
629 gcov_unsigned_t lt_256; /* per 10k with latency <= 256 cycles */
630 gcov_unsigned_t lt_1024; /* per 10k with latency <= 1024 cycles */
631 gcov_unsigned_t gt_1024; /* per 10k with latency > 1024 cycles */
632 gcov_unsigned_t wself; /* weighted average cost of this miss in cycles */
[all...] |
| /prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.6/lib/gcc/mipsel-linux-android/4.6/gcov-src/ |
| gcov-io.h | 62 increments fast enough and cycles slow enough to distinguish
63 different compile/run/compile cycles.
626 gcov_unsigned_t lt_10; /* per 10k with latency <= 10 cycles */
627 gcov_unsigned_t lt_32; /* per 10k with latency <= 32 cycles */
628 gcov_unsigned_t lt_64; /* per 10k with latency <= 64 cycles */
629 gcov_unsigned_t lt_256; /* per 10k with latency <= 256 cycles */
630 gcov_unsigned_t lt_1024; /* per 10k with latency <= 1024 cycles */
631 gcov_unsigned_t gt_1024; /* per 10k with latency > 1024 cycles */
632 gcov_unsigned_t wself; /* weighted average cost of this miss in cycles */
[all...] |
| /prebuilts/gcc/linux-x86/x86/i686-linux-android-4.6/lib/gcc/i686-linux-android/4.6/gcov-src/ |
| gcov-io.h | 62 increments fast enough and cycles slow enough to distinguish
63 different compile/run/compile cycles.
626 gcov_unsigned_t lt_10; /* per 10k with latency <= 10 cycles */
627 gcov_unsigned_t lt_32; /* per 10k with latency <= 32 cycles */
628 gcov_unsigned_t lt_64; /* per 10k with latency <= 64 cycles */
629 gcov_unsigned_t lt_256; /* per 10k with latency <= 256 cycles */
630 gcov_unsigned_t lt_1024; /* per 10k with latency <= 1024 cycles */
631 gcov_unsigned_t gt_1024; /* per 10k with latency > 1024 cycles */
632 gcov_unsigned_t wself; /* weighted average cost of this miss in cycles */
[all...] |
