| /external/proguard/src/proguard/evaluation/value/ |
| InstructionOffsetValue.java | 26 * This class represents a partially evaluated instruction offset. It can
27 * contain 0 or more specific instruction offsets.
69 * Returns whether the given value is present in this list of instruction
90 * Returns the minimum value from this list of instruction offsets.
115 * Returns the maximum value from this list of instruction offsets.
|
| /external/qemu/docs/ |
| CPU-EMULATION.TXT | 13 instruction pointer changes (i.e. at the end of TB execution), a hash
18 another one by tacking an explicit jump instruction.
32 Thumb instructions starting at the current instruction pointer position
33 into a TB. This is done by decomposing each instruction into a series of
45 instruction is translated into a series of host machine instructions that will
|
| /external/smali/dexlib/src/main/java/org/jf/dexlib/Code/Format/ |
| Instruction35c.java | 32 import org.jf.dexlib.Code.Instruction;
45 public static final Instruction.InstructionFactory Factory = new Factory();
99 throw new RuntimeException(String.format("%s index is too large. Use the %s instruction instead.",
165 private static class Factory implements Instruction.InstructionFactory {
166 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex) {
|
| /external/oprofile/events/ppc64/power5++/ |
| events | 32 event:0X0020 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP2 : (Group 2 pm_completion) One or more PPC instruction completed
52 event:0X0052 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP5 : (Group 5 pm_clb2) Marked instruction valid in SRQ
92 event:0X00C0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP12 : (Group 12 pm_prefetch1) Instruction fetched missed L2
93 event:0X00C1 counters:1 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP12 : (Group 12 pm_prefetch1) Cycles at least 1 instruction fetched
101 event:0X00D3 counters:3 um:zero minimum:1000 name:PM_IC_PREF_INSTALL_GRP13 : (Group 13 pm_prefetch2) Instruction prefetched installed in prefetch buffer
104 event:0X00E0 counters:0 um:zero minimum:1000 name:PM_1INST_CLB_CYC_GRP14 : (Group 14 pm_prefetch3) Cycles 1 instruction in CLB
125 event:0X0113 counters:3 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP17 : (Group 17 pm_lsu_reject2) Cycles writing to instruction L1
152 event:0X0160 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_flush2) Instruction TLB misses
201 event:0X01E1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP30 : (Group 30 pm_lsu_stall1) Completion stall caused by LSU instruction
213 event:0X0201 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP32 : (Group 32 pm_fxu_stall) Completion stall caused by FXU instruction
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombinePHI.cpp | 24 Instruction *InstCombiner::FoldPHIArgBinOpIntoPHI(PHINode &PN) {
25 Instruction *FirstInst = cast<Instruction>(PN.getIncomingValue(0));
45 Instruction *I = dyn_cast<Instruction>(PN.getIncomingValue(i));
101 Instruction *InInst = cast<Instruction>(PN.getIncomingValue(i));
130 Instruction *InstCombiner::FoldPHIArgGEPIntoPHI(PHINode &PN) {
287 Instruction *InstCombiner::FoldPHIArgLoadIntoPHI(PHINode &PN) {
391 Instruction *InstCombiner::FoldPHIArgOpIntoPHI(PHINode &PN)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 145 virtual bool TargetSelectInstruction(const Instruction *I);
154 // Instruction selection routines.
156 bool SelectLoad(const Instruction *I);
157 bool SelectStore(const Instruction *I);
158 bool SelectBranch(const Instruction *I);
159 bool SelectIndirectBr(const Instruction *I);
160 bool SelectCmp(const Instruction *I);
161 bool SelectFPExt(const Instruction *I);
162 bool SelectFPTrunc(const Instruction *I);
163 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode)
[all...] |
| /external/llvm/lib/Bitcode/Writer/ |
| BitcodeWriter.cpp | 71 default: llvm_unreachable("Unknown cast instruction!");
72 case Instruction::Trunc : return bitc::CAST_TRUNC;
73 case Instruction::ZExt : return bitc::CAST_ZEXT;
74 case Instruction::SExt : return bitc::CAST_SEXT;
75 case Instruction::FPToUI : return bitc::CAST_FPTOUI;
76 case Instruction::FPToSI : return bitc::CAST_FPTOSI;
77 case Instruction::UIToFP : return bitc::CAST_UITOFP;
78 case Instruction::SIToFP : return bitc::CAST_SITOFP;
79 case Instruction::FPTrunc : return bitc::CAST_FPTRUNC;
80 case Instruction::FPExt : return bitc::CAST_FPEXT
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 47 /// instruction info tracks.
221 // Instruction encodings. These are the standard/most common forms for X86
225 // PseudoFrm - This represents an instruction that is a pseudo instruction
284 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
300 // OpSize - Set if this instruction requires an operand size prefix (0x66),
301 // which most often indicates that the instruction operates on 16 bit data
305 // AsSize - Set if this instruction requires an operand size prefix (0x67),
306 // which most often indicates that the instruction address 16 bit address
319 // TB - TwoByte - Set if this instruction has a two byte opcode, whic
[all...] |
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/ |
| yasm_arch.xml | 83 instruction set and derivatives and the AMD64 instruction set. It
96 the x86 instruction set contains portions whose function is
158 ch, and bh with an instruction that requires the REX prefix for
163 <para>(NASM syntax) is not a legal instruction because the use of
181 <screen>mov eax, 1 ; 32-bit instruction</screen>
182 <screen>mov rcx, 1 ; 64-bit instruction</screen>
189 <screen>push eax ; illegal instruction</screen>
190 <screen>push rbx ; 1-byte instruction</screen>
191 <screen>push r11 ; 2-byte instruction with REX prefix</screen
[all...] |
| /external/chromium_org/third_party/yasm/source/patched-yasm/ |
| yasm_arch.7 | 51 architecture supports the IA\-32 instruction set and derivatives and the AMD64 instruction set\&. It consists of two machines:
62 The x86 architecture BITS setting specifies to Yasm the processor mode in which the generated code is intended to execute\&. x86 processors can run in three different major execution modes: 16\-bit, 32\-bit, and on AMD64\-supporting processors, 64\-bit\&. As the x86 instruction set contains portions whose function is execution\-mode dependent (such as operand\-size and address\-size override prefixes), Yasm cannot assemble x86 instructions correctly unless it is told by the user in what processor mode the code will execute\&.
93 New 8\-bit registers are also available that map to the 8 least significant bits of rsi, rdi, rsp, and rbp\&. These are called sil, dil, spl, and bpl respectively\&. Unfortunately, due to the way instructions are encoded, these new 8\-bit registers are encoded the same as the old 8\-bit registers ah, dh, ch, and bh\&. The processor tells which is being used by the presence of the new REX prefix that is used to specify the other extended registers\&. This means it is illegal to mix the use of ah, dh, ch, and bh with an instruction that requires the REX prefix for other reasons\&. For instance:
105 (NASM syntax) is not a legal instruction because the use of r10 requires a REX prefix, making it impossible to use ah\&.
126 mov eax, 1 ; 32\-bit instruction
136 mov rcx, 1 ; 64\-bit instruction
148 push eax ; illegal instruction
158 push rbx ; 1\-byte instruction
168 push r11 ; 2\-byte instruction with REX prefi
[all...] |
| /external/llvm/lib/Analysis/ |
| MemoryBuiltins.cpp | 192 /// extractMallocCall - Returns the corresponding CallInst if the instruction
226 /// isArrayMalloc - Returns the corresponding CallInst if the instruction
299 /// extractCallocCall - Returns the corresponding CallInst if the instruction
401 if (Instruction *I = dyn_cast<Instruction>(V)) {
402 // If we have already seen this instruction, bail out. Cycles can happen in
422 if (CE->getOpcode() == Instruction::IntToPtr)
424 if (CE->getOpcode() == Instruction::GetElementPtr)
576 SizeOffsetType ObjectSizeOffsetVisitor::visitInstruction(Instruction &I) {
577 DEBUG(dbgs() << "ObjectSizeOffsetVisitor unknown instruction:" << I << '\n')
[all...] |
| /external/llvm/lib/Transforms/Instrumentation/ |
| ThreadSanitizer.cpp | 91 bool instrumentLoadOrStore(Instruction *I);
92 bool instrumentAtomic(Instruction *I);
93 bool instrumentMemIntrinsic(Instruction *I);
94 void chooseInstructionsToInstrument(SmallVectorImpl<Instruction*> &Local,
95 SmallVectorImpl<Instruction*> &All);
242 static bool isVtableAccess(Instruction *I) {
285 SmallVectorImpl<Instruction*> &Local,
286 SmallVectorImpl<Instruction*> &All) {
289 for (SmallVectorImpl<Instruction*>::reverse_iterator It = Local.rbegin(),
291 Instruction *I = *It
[all...] |
| /frameworks/compile/slang/BitWriter_3_2/ |
| BitcodeWriter.cpp | 70 default: llvm_unreachable("Unknown cast instruction!");
71 case Instruction::Trunc : return bitc::CAST_TRUNC;
72 case Instruction::ZExt : return bitc::CAST_ZEXT;
73 case Instruction::SExt : return bitc::CAST_SEXT;
74 case Instruction::FPToUI : return bitc::CAST_FPTOUI;
75 case Instruction::FPToSI : return bitc::CAST_FPTOSI;
76 case Instruction::UIToFP : return bitc::CAST_UITOFP;
77 case Instruction::SIToFP : return bitc::CAST_SITOFP;
78 case Instruction::FPTrunc : return bitc::CAST_FPTRUNC;
79 case Instruction::FPExt : return bitc::CAST_FPEXT
[all...] |
| /external/llvm/docs/ |
| CodeGenerator.rst | 91 does not require register allocation, instruction selection, or any of the other
113 1. `Instruction Selection`_ --- This phase determines an efficient way to
114 express the input LLVM code in the target instruction set. This stage
115 produces the initial code for the program in the target instruction set, then
122 instructions produced by the instruction selection phase, determines an
125 describe this in the `instruction selection section`_ because it operates on
130 the instruction selector. Optimizations like modulo-scheduling or peephole
153 The code generator is based on the assumption that the instruction selector will
172 information (e.g., an ``add`` instruction is almost identical to a ``sub``
173 instruction). In order to allow the maximum amount of commonality to b
[all...] |
| ProgrammersManual.rst | 134 // Otherwise, it must be an instruction...
135 return !L->contains(cast<Instruction>(V)->getParent());
164 efficient to use the ``InstVisitor`` class to dispatch over the instruction
242 a common LLVM paradigm is to name one instruction based on the name of another
243 instruction with a suffix, for example:
356 instruction scheduling to be enabled with ``-debug-type=InstrSched``, even if
437 49 cee - Number of setcc instruction eliminated
461 :ref:`MachineBasicBlocks <MachineBasicBlock>`, and :ref:`Instruction Selection
738 These properties are exactly what we want for things like ``Instruction``\ s and
[all...] |
| /art/runtime/entrypoints/portable/ |
| portable_throw_entrypoints.cc | 121 const Instruction* first_catch_instr = Instruction::At(&mh.GetCodeItem()->insns_[catch_dex_pc]);
122 if (first_catch_instr->Opcode() != Instruction::MOVE_EXCEPTION) {
|
| /art/runtime/verifier/ |
| register_line.cc | 91 const RegType& RegisterLine::GetInvocationThis(const Instruction* inst, bool is_range) {
282 void RegisterLine::CheckUnaryOp(const Instruction* inst,
290 void RegisterLine::CheckUnaryOpWide(const Instruction* inst,
298 void RegisterLine::CheckUnaryOpToWide(const Instruction* inst,
306 void RegisterLine::CheckUnaryOpFromWide(const Instruction* inst,
314 void RegisterLine::CheckBinaryOp(const Instruction* inst,
334 void RegisterLine::CheckBinaryOpWide(const Instruction* inst,
344 void RegisterLine::CheckBinaryOpWideShift(const Instruction* inst,
353 void RegisterLine::CheckBinaryOp2addr(const Instruction* inst,
372 void RegisterLine::CheckBinaryOp2addrWide(const Instruction* inst
[all...] |
| /dalvik/vm/mterp/armv5te/ |
| OP_CMP_LONG.S | 21 * instruction epilogue code. The multi-compare approach below needs
50 GOTO_OPCODE(ip) @ jump to next instruction
60 GOTO_OPCODE(ip) @ jump to next instruction
|
| OP_EXECUTE_INLINE_RANGE.S | 4 * Execute a "native inline" instruction, using "/range" semantics.
31 GOTO_OPCODE(ip) @ jump to next instruction
87 GOTO_OPCODE(ip) @ jump to next instruction
|
| OP_NEW_INSTANCE.S | 40 * include this instruction in a trace.
53 GOTO_OPCODE(ip) @ jump to next instruction
73 GOTO_OPCODE(ip) @ jump to next instruction
|
| /dalvik/vm/mterp/mips/ |
| OP_EXECUTE_INLINE.S | 4 * Execute a "native inline" instruction.
33 GOTO_OPCODE(t0) # jump to next instruction
104 GOTO_OPCODE(t0) # jump to next instruction
|
| OP_EXECUTE_INLINE_RANGE.S | 4 * Execute a "native inline" instruction, using "/range" semantics.
29 GOTO_OPCODE(t0) # jump to next instruction
92 GOTO_OPCODE(t0) # jump to next instruction
|
| OP_NEW_INSTANCE.S | 39 * include this instruction in a trace.
57 GOTO_OPCODE(t0) # jump to next instruction
77 GOTO_OPCODE(t0) # jump to next instruction
|
| /external/chromium/base/ |
| atomicops_internals_x86_gcc.cc | 19 // Inline cpuid instruction. In PIC compilations, %ebx contains the address
72 // instruction doesn't act as a read-acquire barrier if followed by a
73 // non-locked read-modify-write instruction. Rev F has this bug in
|
| /external/chromium_org/base/ |
| atomicops_internals_x86_gcc.cc | 19 // Inline cpuid instruction. In PIC compilations, %ebx contains the address
72 // instruction doesn't act as a read-acquire barrier if followed by a
73 // non-locked read-modify-write instruction. Rev F has this bug in
|
