| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 231 /// they are just a fixed opcode value, like 'leave'.
235 /// their one register operand added to their opcode.
259 /// a Mod/RM byte, and use the middle field to hold extended opcode
314 // set, there is no prefix byte for obtaining a multibyte opcode.
319 // TB - TwoByte - Set if this instruction has a two byte opcode, which
320 // starts with a 0x0F byte before the real opcode.
412 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
433 /// VEX - The opcode prefix used by AVX instructions
437 /// VEX_W - Has a opcode specific functionality, but is used in the same
455 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the curren
[all...] |
| X86MCCodeEmitter.cpp | 527 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
539 // VEX_R: opcode externsion equivalent to REX.R in
562 // VEX_W: opcode specific (use like REX.W, or used for
563 // opcode extension, or ignored, depending on the opcode byte)
572 // 0b00001: implied 0F leading opcode
573 // 0b00010: implied 0F 38 leading opcode bytes
574 // 0b00011: implied 0F 3A leading opcode bytes
593 // VEX_PP: opcode extension providing equivalent
615 // Encode the operand size opcode prefix as needed
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 235 /// opcode and if it only has one use.
236 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode) {
238 cast<Instruction>(V)->getOpcode() == Opcode)
349 static void IncorporateWeight(APInt &LHS, const APInt &RHS, unsigned Opcode) {
367 if (Instruction::isIdempotent(Opcode)) {
374 if (Instruction::isNilpotent(Opcode)) {
380 if (Opcode == Instruction::Add) {
386 assert(Opcode == Instruction::Mul && "Unknown associative operation!");
444 /// opcode), or is the same kind of binary operator but has a use which either
501 unsigned Opcode = I->getOpcode()
[all...] |
| /art/compiler/dex/quick/ |
| gen_common.cc | 86 void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1,
90 switch (opcode) {
111 LOG(FATAL) << "Unexpected opcode " << opcode;
140 void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken,
144 switch (opcode) {
165 LOG(FATAL) << "Unexpected opcode " << opcode;
182 void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest,
187 switch (opcode) {
[all...] |
| /external/javassist/src/main/javassist/ |
| CtClass.java | 30 import javassist.bytecode.Opcode;
133 "booleanValue", "()Z", Opcode.IRETURN,
134 Opcode.T_BOOLEAN, 1);
138 "charValue", "()C", Opcode.IRETURN,
139 Opcode.T_CHAR, 1);
143 "byteValue", "()B", Opcode.IRETURN,
144 Opcode.T_BYTE, 1);
148 "shortValue", "()S", Opcode.IRETURN,
149 Opcode.T_SHORT, 1);
153 "intValue", "()I", Opcode.IRETURN
[all...] |
| /external/javassist/src/main/javassist/bytecode/ |
| CodeIterator.java | 34 public class CodeIterator implements Opcode {
174 * (not the operand following the current opcode).
733 * Calculates the index of the next opcode.
738 int opcode; local
740 opcode = code[index] & 0xff;
743 throw new BadBytecode("invalid opcode address");
747 int len = opcodeLength[opcode];
750 else if (opcode == WIDE)
757 if (opcode == LOOKUPSWITCH) {
761 else if (opcode == TABLESWITCH)
1413 int opcode(int op) { method in class:CodeIterator.If16
[all...] |
| /external/javassist/src/main/javassist/compiler/ |
| CodeGen.java | 28 public abstract class CodeGen extends Visitor implements Opcode, TokenId {
61 protected abstract boolean doit(Bytecode b, int opcode);
294 bytecode.addOpcode(Opcode.RETURN);
396 bytecode.addOpcode(Opcode.GOTO);
423 bytecode.addOpcode(Opcode.GOTO);
485 bytecode.addOpcode(Opcode.GOTO);
579 bytecode.addOpcode(Opcode.GOTO);
595 op = Opcode.RETURN;
657 protected boolean doit(Bytecode b, int opcode) {
673 bc.addOpcode(Opcode.GOTO)
[all...] |
| /external/valgrind/main/VEX/useful/ |
| hd_fpu.c | 723 /* bits 5,4,3 are an opcode extension, and the modRM also
777 /* The entire modRM byte is an opcode extension. */
823 /* bits 5,4,3 are an opcode extension, and the modRM also
876 /* The entire modRM byte is an opcode extension. */
[all...] |
| /art/compiler/dex/quick/x86/ |
| int_x86.cc | 101 // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode
407 X86OpCode opcode = kX86Bkpt; local
409 case kOpCmp: opcode = kX86Cmp32RT; break;
410 case kOpMov: opcode = kX86Mov32RT; break;
412 LOG(FATAL) << "Bad opcode: " << op;
415 NewLIR2(opcode, r_dest, thread_offset.Int32Value());
561 void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
564 GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift);
567 void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode,
570 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2)
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| SCCP.java | 241 Rop opcode = insn.getOpcode(); local
248 if (opcode.getBranchingness() == Rop.BRANCH_IF) {
274 switch (opcode.getOpcode()) {
306 switch (opcode.getOpcode()) {
367 int opcode = insn.getOpcode().getOpcode(); local
404 switch (opcode) {
476 int opcode = insn.getOpcode().getOpcode(); local
481 if (opcode == RegOps.DIV || opcode == RegOps.REM) {
493 switch (opcode) {
[all...] |
| /dalvik/vm/compiler/codegen/x86/libenc/ |
| enc_base.h | 146 * Description of an operand in opcode - its kind, size or RegName if
217 * @brief Info about single opcode - its opcode bytes, operands,
225 * @brief Raw opcode bytes.
227 * 'Raw' opcode bytes which do not require any analysis and are
228 * independent from arguments/sizes/etc (may include opcode size
231 char opcode[5];
236 * @brief Info about opcode's operands.
295 * @brief Empty value, used in hash-to-opcode map to show an empty slot.
602 * @brief Encodes special things of opcode description - '/r', 'ib', etc
[all...] |
| /external/chromium_org/third_party/WebKit/Tools/Scripts/webkitpy/thirdparty/coverage/ |
| parser.py | 3 import opcode, re, sys, token, tokenize namespace
261 """Return the opcode by name from the opcode module."""
262 return opcode.opmap[name]
455 # Look at the opcode
461 # The opcode has a jump, it's an exit for this chunk.
465 # The opcode can exit the code object.
468 # The opcode adds a block to the block_stack.
471 # The opcode pops a block from the block stack.
474 # This opcode forces the end of the chunk
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/main/ |
| atifragshader.c | 414 GLuint op = curProg->SetupInst[j][i].Opcode;
422 GLuint op0 = curProg->Instructions[j][i].Opcode[0];
423 GLuint op1 = curProg->Instructions[j][i].Opcode[1];
503 curI->Opcode = ATI_FRAGMENT_SHADER_PASS_OP;
576 curI->Opcode = ATI_FRAGMENT_SHADER_SAMPLE_OP;
646 if (((op == GL_DOT2_ADD_ATI) && (curI->Opcode[0] != GL_DOT2_ADD_ATI)) ||
647 ((op == GL_DOT3_ATI) && (curI->Opcode[0] != GL_DOT3_ATI)) ||
648 ((op == GL_DOT4_ATI) && (curI->Opcode[0] != GL_DOT4_ATI)) ||
649 ((op != GL_DOT4_ATI) && (curI->Opcode[0] == GL_DOT4_ATI))) {
683 curI->Opcode[optype] = op
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| SCCP.java | 242 Rop opcode = insn.getOpcode(); local
249 if (opcode.getBranchingness() == Rop.BRANCH_IF) {
275 switch (opcode.getOpcode()) {
307 switch (opcode.getOpcode()) {
368 int opcode = insn.getOpcode().getOpcode(); local
405 switch (opcode) {
477 int opcode = insn.getOpcode().getOpcode(); local
482 if (opcode == RegOps.DIV || opcode == RegOps.REM) {
494 switch (opcode) {
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrNEON.td | 48 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size, bits<5> opcode,
54 def _8B : NeonI_3VSame<0b0, u, size, opcode,
61 def _16B : NeonI_3VSame<0b1, u, size, opcode,
71 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
76 def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
83 def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
90 def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
97 def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
105 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
108 : NeonI_3VSame_HS_sizes<u, opcode, asmop, opnode, Commutable
[all...] |
| /external/mesa3d/src/mesa/main/ |
| atifragshader.c | 414 GLuint op = curProg->SetupInst[j][i].Opcode;
422 GLuint op0 = curProg->Instructions[j][i].Opcode[0];
423 GLuint op1 = curProg->Instructions[j][i].Opcode[1];
503 curI->Opcode = ATI_FRAGMENT_SHADER_PASS_OP;
576 curI->Opcode = ATI_FRAGMENT_SHADER_SAMPLE_OP;
646 if (((op == GL_DOT2_ADD_ATI) && (curI->Opcode[0] != GL_DOT2_ADD_ATI)) ||
647 ((op == GL_DOT3_ATI) && (curI->Opcode[0] != GL_DOT3_ATI)) ||
648 ((op == GL_DOT4_ATI) && (curI->Opcode[0] != GL_DOT4_ATI)) ||
649 ((op != GL_DOT4_ATI) && (curI->Opcode[0] == GL_DOT4_ATI))) {
683 curI->Opcode[optype] = op
[all...] |
| /bionic/libc/netbsd/resolv/ |
| res_debug.c | 166 ns_opcode opcode; local
182 opcode = (ns_opcode) ns_msg_getflag(*handle, ns_f_opcode);
196 p_section(section, opcode));
245 u_int opcode, rcode, id; local
251 opcode = ns_msg_getflag(handle, ns_f_opcode);
264 ";; ->>HEADER<<- opcode: %s, status: %s, id: %d\n",
265 _res_opcodes[opcode], p_rcode((int)rcode), id);
289 p_section(ns_s_qd, (int)opcode), qdcount);
291 p_section(ns_s_an, (int)opcode), ancount);
293 p_section(ns_s_ns, (int)opcode), nscount)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.td | 343 // looking at the opcode). This means that the default operand matching logic
587 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
591 def NAME : XForm_6<opcode, xo, OOL, IOL,
595 def o : XForm_6<opcode, xo, OOL, IOL,
601 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
606 def NAME : XForm_6<opcode, xo, OOL, IOL,
610 def o : XForm_6<opcode, xo, OOL, IOL,
616 multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
620 def NAME : XForm_10<opcode, xo, OOL, IOL,
624 def o : XForm_10<opcode, xo, OOL, IOL
[all...] |
| /dalvik/vm/interp/ |
| Interp.cpp | 85 u1 originalOpcode; /* original 8-bit opcode value */
182 * Retrieve the opcode that was originally at the specified location.
186 * Returns "true" with the opcode in *pOrig on success.
200 * Check the opcode. If it's a "magic" NOP, indicating the start of
226 * For a new entry, this will extract and preserve the current opcode from
227 * the instruction stream, and replace it with a breakpoint opcode.
264 * Change the opcode. We must ensure that the BreakpointSet
265 * updates happen before we change the opcode.
273 * The class init code will "flush" all pending opcode writes
307 * opcode is restored
848 u2 opcode = GET_OPCODE(*pc); local
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.cpp | 139 unsigned int getDstOpndCount(enum sm4_opcode opcode) const;
495 Converter::getDstOpndCount(enum sm4_opcode opcode) const
497 switch (opcode) {
850 switch (dcl.opcode) {
[all...] |
| /external/emma/core/java12/com/vladium/emma/instr/ |
| InstrVisitor.java | 745 final int opcode = 0xFF & code [ip]; local
748 //if (trace3) m_log.trace3 ("parse", MNEMONICS [opcode]);
749 // "visitor.visit (opcode, wide, ip, null)":
751 { // "opcode visit" logic:
762 switch (opcode)
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.cpp | 139 unsigned int getDstOpndCount(enum sm4_opcode opcode) const;
495 Converter::getDstOpndCount(enum sm4_opcode opcode) const
497 switch (opcode) {
850 switch (dcl.opcode) {
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| DalvOps.java | 20 * All the Dalvik opcode value constants. See the related spec
21 * document for the meaning and instruction format of each opcode.
24 /** pseudo-opcode used for nonstandard format "instructions" */
27 /** minimum valid opcode value */
30 /** maximum valid opcode value */
33 // BEGIN(opcodes); GENERATED AUTOMATICALLY BY opcode-gen
|
| /dalvik/dx/src/com/android/dx/dex/file/ |
| DebugInfoDecoder.java | 294 int opcode = bs.readByte() & 0xff; local
296 switch (opcode) {
399 if (opcode < DBG_FIRST_SPECIAL) {
401 "Invalid extended opcode encountered "
402 + opcode);
405 int adjopcode = opcode - DBG_FIRST_SPECIAL;
|
| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| Gen.cpp | 65 int opcode = TEMPLATE_PERIODIC_PROFILING; local
67 (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
68 (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
70 (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
71 (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
349 if (mir->dalvikInsn.opcode == OP_MONITOR_ENTER)
|
