| /external/mesa3d/src/mesa/main/ |
| blend.c | 620 * \param opcode operation.
622 * Verifies that \p opcode is a valid enum and updates
628 _mesa_LogicOp( GLenum opcode )
634 _mesa_debug(ctx, "glLogicOp(%s)\n", _mesa_lookup_enum_by_nr(opcode));
636 switch (opcode) {
659 if (ctx->Color.LogicOp == opcode)
663 ctx->Color.LogicOp = opcode;
666 ctx->Driver.LogicOpcode( ctx, opcode );
|
| /external/open-vcdiff/src/ |
| decodetable.h | 85 // or VCD_INSTRUCTION_END_OF_DATA if the end of the opcode stream is reached,
95 // Any occurrences of VCD_NOOP in the opcode stream
|
| /external/proguard/src/proguard/evaluation/ |
| Processor.java | 79 switch (simpleInstruction.opcode)
550 throw new IllegalArgumentException("Unknown simple instruction ["+simpleInstruction.opcode+"]");
559 switch (constantInstruction.opcode)
629 throw new IllegalArgumentException("Unknown constant pool instruction ["+constantInstruction.opcode+"]");
638 switch (variableInstruction.opcode)
741 throw new IllegalArgumentException("Unknown variable instruction ["+variableInstruction.opcode+"]");
750 switch (branchInstruction.opcode)
[all...] |
| /external/valgrind/main/VEX/priv/ |
| guest_mips_toIR.c | 462 UInt opcode = get_opcode(cins); local
467 if (opcode == 0x07 || opcode == 0x06 || opcode == 0x05 || opcode == 0x04
468 || opcode == 0x03 || opcode == 0x02) {
473 if (opcode == 0x01 && rt == 0x01) {
478 if (opcode == 0x01 && rt == 0x11) {
483 if (opcode == 0x01 && rt == 0x10)
517 UInt opcode = get_opcode(cins); local
547 UInt opcode = get_opcode(cins); local
1201 UInt opcode, cins, rs, rt, rd, sa, ft, fs, fd, fmt, tf, nd, function, local
[all...] |
| /hardware/ti/wlan/mac80211/ti-utils/uim_rfkill/ |
| uim.c | 264 static int read_command_complete(int fd, unsigned short opcode)
300 if (resp.cmd_complete.opcode != (unsigned short)opcode) {
301 UIM_ERR(" Error in response: opcode is 0x%04x, not 0x%04x!",
302 resp.cmd_complete.opcode, opcode);
453 cmd.hci_hdr.opcode = HCI_HDR_OPCODE;
491 addr_cmd.hci_hdr.opcode = WRITE_BD_ADDR_OPCODE;
|
| /hardware/ti/wpan/ti_st/uim-sysfs/ |
| uim.c | 202 static int read_command_complete(int fd, unsigned short opcode)
238 if (resp.cmd_complete.opcode != (unsigned short)opcode) {
239 UIM_ERR(" Error in response: opcode is 0x%04x, not 0x%04x!",
240 resp.cmd_complete.opcode, opcode);
436 cmd.hci_hdr.opcode = HCI_HDR_OPCODE;
473 addr_cmd.hci_hdr.opcode = WRITE_BD_ADDR_OPCODE;
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/arpa/ |
| nameser_compat.h | 53 unsigned opcode: 4; /* purpose of message */ member in struct:__anon37233
69 unsigned opcode :4; /* purpose of message */ member in struct:__anon37233
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm-generic/ |
| siginfo.h | 146 #define ILL_ILLOPC (__SI_FAULT|1) /* illegal opcode */
150 #define ILL_PRVOPC (__SI_FAULT|5) /* privileged opcode */
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/arpa/ |
| nameser_compat.h | 53 unsigned opcode: 4; /* purpose of message */ member in struct:__anon38823
69 unsigned opcode :4; /* purpose of message */ member in struct:__anon38823
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/asm-generic/ |
| siginfo.h | 146 #define ILL_ILLOPC (__SI_FAULT|1) /* illegal opcode */
150 #define ILL_PRVOPC (__SI_FAULT|5) /* privileged opcode */
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/arpa/ |
| nameser_compat.h | 53 unsigned opcode: 4; /* purpose of message */ member in struct:__anon40338
69 unsigned opcode :4; /* purpose of message */ member in struct:__anon40338
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/asm-generic/ |
| siginfo.h | 146 #define ILL_ILLOPC (__SI_FAULT|1) /* illegal opcode */
150 #define ILL_PRVOPC (__SI_FAULT|5) /* privileged opcode */
|
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/ |
| dis.py | 6 from opcode import *
7 from opcode import __all__ as _opcodes_all
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/ |
| dis.py | 6 from opcode import *
7 from opcode import __all__ as _opcodes_all
|
| /external/chromium-trace/trace-viewer/third_party/pywebsocket/src/test/ |
| client_for_testing.py | 236 opcode = first_byte & 0xf
257 return fin, rsv1, rsv2, rsv3, opcode, payload_length
788 opcode = OPCODE_CONTINUATION
790 opcode = frame_type
808 header = chr(fin << 7 | rsv1 << 6 | opcode)
828 def _assert_receive_data(self, payload, opcode, fin, rsv1, rsv2, rsv3):
832 if actual_opcode != opcode:
834 'Unexpected opcode: %d (expected) vs %d (actual)' %
835 (opcode, actual_opcode))
883 def assert_receive_binary(self, payload, opcode=OPCODE_BINARY, fin=1
[all...] |
| /external/proguard/src/proguard/optimize/evaluation/ |
| EvaluationShrinker.java | 200 if (instruction.opcode == InstructionConstants.OP_GOTO &&
483 switch (constantInstruction.opcode)
566 switch (simpleInstruction.opcode)
618 if (variableInstruction.opcode < InstructionConstants.OP_ISTORE)
632 if (constantInstruction.opcode == InstructionConstants.OP_NEW)
646 if (branchInstruction.opcode == InstructionConstants.OP_JSR ||
647 branchInstruction.opcode == InstructionConstants.OP_JSR_W)
[all...] |
| /external/qemu/target-mips/ |
| translate.c | 45 /* indirect opcode tables */
117 /* Reserved major opcode */
465 uint32_t opcode; member in struct:DisasContext
507 ctx->pc, ctx->opcode , ## __VA_ARGS__)
516 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
517 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
835 opcode tables. */
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.h | 481 void EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct);
482 void EmitI(int opcode, Register rs, Register rt, uint16_t imm);
483 void EmitJ(int opcode, int address);
484 void EmitFR(int opcode, int fmt, FRegister ft, FRegister fs, FRegister fd, int funct);
485 void EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm);
|
| /external/bluetooth/bluedroid/stack/mcap/ |
| mca_main.c | 44 /* table of standard opcode message size */
458 /* all the request opcode has bit 0 set. response code has bit 0 clear */
466 MCA_TRACE_ERROR3 ("opcode: %d required len:%d, got len:%d", *p, mca_std_msg_len[*p], p_buf->len);
472 MCA_TRACE_ERROR2 ("unsupported SYNC opcode: %d len:%d", *p, p_buf->len);
478 MCA_TRACE_ERROR2 ("bad opcode: %d len:%d", *p, p_buf->len);
|
| /external/chromium_org/net/websockets/ |
| websocket_channel.h | 72 WebSocketFrameHeader::OpCode op_code,
187 ChannelState HandleFrame(const WebSocketFrameHeader::OpCode opcode,
196 // opcode.
198 WebSocketFrameHeader::OpCode op_code,
|
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_soa.c | 938 enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
1379 unsigned opcode; local
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/ |
| tgsi_dump.c | 487 const struct tgsi_opcode_info *info = tgsi_get_opcode_info( inst->Instruction.Opcode );
598 switch (inst->Instruction.Opcode) {
610 if (inst->Instruction.Opcode == TGSI_OPCODE_IF ||
611 inst->Instruction.Opcode == TGSI_OPCODE_ELSE ||
612 inst->Instruction.Opcode == TGSI_OPCODE_BGNLOOP) {
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/intel/ |
| intel_blit.c | 408 uint32_t opcode, br13, blit_cmd; local
435 opcode = XY_SETUP_BLT_CMD;
437 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
440 opcode |= XY_DST_TILED;
453 OUT_BATCH(opcode);
|
| /external/chromium_org/third_party/sqlite/src/src/ |
| bitvec.c | 308 ** by 0, 1, or 3 operands, depending on the opcode. Another
309 ** opcode follows immediately after the last operand.
312 ** "halt" opcode and causes the test to end.
323 ** Opcode 5 works on the linear array only, not on the Bitvec.
324 ** Opcode 5 is used to deliberately induce a fault in order to
|
| /external/javassist/tutorial/ |
| tutorial3.html | 143 <em>Note that it does not return the opcode of the next
164 System.out.println(Mnemonic.OPCODE[op]);
202 <code>addOpcode()</code> for adding an 8bit opcode and
204 The 8bit value of each opcode is defined in the <code>Opcode</code>
|
