| /external/llvm/lib/Target/X86/ |
| X86InstrCMovSetCC.td | 1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
16 // SetCC instructions.
81 // SetCC instructions.
82 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
95 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
96 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
97 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
98 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
99 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
100 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal t
[all...] |
| X86TargetTransformInfo.cpp | 470 { ISD::SETCC, MVT::v2f64, 1 },
471 { ISD::SETCC, MVT::v4f32, 1 },
472 { ISD::SETCC, MVT::v2i64, 1 },
473 { ISD::SETCC, MVT::v4i32, 1 },
474 { ISD::SETCC, MVT::v8i16, 1 },
475 { ISD::SETCC, MVT::v16i8, 1 },
479 { ISD::SETCC, MVT::v4f64, 1 },
480 { ISD::SETCC, MVT::v8f32, 1 },
482 { ISD::SETCC, MVT::v4i64, 4 },
483 { ISD::SETCC, MVT::v8i32, 4 }
[all...] |
| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 111 COMPARE(and_(r2, r3, Operand(r4), SetCC),
118 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
122 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
127 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
131 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
138 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
147 COMPARE(add(r7, r8, Operand(ip), SetCC),
149 COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
156 COMPARE(adc(r5, sp, Operand(ip), SetCC),
158 COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc)
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| setcc-takes-i32.ll | 4 ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output,
8 ; It was expecting the smallest legal promotion of i1 to be the preferred SetCC
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm.cc | 107 COMPARE(and_(r2, r3, Operand(r4), SetCC),
114 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
118 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
123 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
127 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
134 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
143 COMPARE(add(r7, r8, Operand(ip), SetCC),
145 COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
152 COMPARE(adc(r5, sp, Operand(ip), SetCC),
154 COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc)
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| sitofp-selectcc-opt.ll | 8 ; (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
|
| /external/llvm/test/CodeGen/R600/ |
| legalizedag-bug-expand-setcc.ll | 5 ; setcc to select_cc.
|
| fcmp.ll | 17 ; This test checks that a setcc node with f32 operands is lowered to a
|
| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| exit_compare_live_range.ll | 2 ; having overlapping live ranges that result in copies. We want the setcc
|
| /external/llvm/test/Transforms/ConstProp/ |
| 2002-09-03-SetCC-Bools.ll | 0 ; SetCC on boolean values was not implemented!
|
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
398 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
[all...] |
| /external/chromium_org/third_party/icu/source/tools/gennorm2/ |
| n2builder.h | 59 void setCC(UChar32 c, uint8_t cc);
|
| /external/icu4c/tools/gennorm2/ |
| n2builder.h | 59 void setCC(UChar32 c, uint8_t cc);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXVector.td | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC);
318 ISD::SETCC,
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
403 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
415 case ISD::SETCC: {
422 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
| SIInstructions.td | 85 [(set SCCReg:$dst, (setcc SReg_32:$src0, imm:$src1, SETEQ))]
111 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LT))]
114 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_EQ))]
117 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LE))]
120 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GT))]
123 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))]
126 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GE))]
135 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))]
254 [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETEQ))]
259 [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETNE))
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC);
318 ISD::SETCC,
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
403 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
415 case ISD::SETCC: {
422 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
| SIInstructions.td | 85 [(set SCCReg:$dst, (setcc SReg_32:$src0, imm:$src1, SETEQ))]
111 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LT))]
114 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_EQ))]
117 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LE))]
120 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GT))]
123 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))]
126 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GE))]
135 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))]
254 [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETEQ))]
259 [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETNE))
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 78 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
79 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
92 setTargetDAGCombine(ISD::SETCC);
431 if (Intr->getOpcode() == ISD::SETCC) {
433 SDNode *SetCC = Intr;
434 assert(SetCC->getConstantOperandVal(1) == 1);
435 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
437 Intr = SetCC->getOperand(0).getNode();
513 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
560 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 70 /// which will be produced by a setcc instruction.
73 /// This serves most of the functions of the LLVM SETCC instruction, for two
81 SETCC,
|
| AArch64ISelLowering.cpp | 114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
232 setOperationAction(ISD::SETCC, MVT::f128, Custom);
285 setOperationAction(ISD::SETCC, MVT::v8i8, Custom);
286 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
287 setOperationAction(ISD::SETCC, MVT::v4i16, Custom);
288 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
289 setOperationAction(ISD::SETCC, MVT::v2i32, Custom)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2004-11-27-SetCCForCastLargerAndConstant.ll | 8 ; cast operands, and types of setCC operators. In all cases, the cast should
9 ; be eliminated. In many cases the setCC is also eliminated based on the
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 73 setTargetDAGCombine(ISD::SETCC);
481 SDValue SetCC = N->getOperand(0);
483 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
487 SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
488 N->getOperand(2), SetCC.getOperand(2));
511 case ISD::SETCC: {
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 101 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
107 && "Unsupported setcc type!");
179 default: llvm_unreachable("Do not know how to soften this setcc!");
190 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
194 NewLHS = DAG.getNode(ISD::SETCC, dl,
[all...] |
