| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 203 MachineInstrBuilder MIB(*MF, MI);
204 MIB.addReg(DstReg, RegState::Define);
205 MIB.addImm(Imm);
|
| AMDILCFGStructurizer.cpp | 504 MachineInstrBuilder MIB(*MF, NewMI);
505 MIB.addReg(OldMI->getOperand(1).getReg(), false);
[all...] |
| R600ISelLowering.cpp | 466 MachineInstrBuilder MIB(*MF, MI);
468 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 165 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
168 MIB.addReg(DestReg, RegState::Define);
171 MIB.addReg(SrcReg, getKillRegState(KillSrc));
174 MIB.addReg(ZeroReg);
497 MachineInstrBuilder MIB = genInstrWithNewOpc(OpcS, I);
498 MIB->getOperand(0).setReg(LoReg);
502 MIB = genInstrWithNewOpc(OpcS, I);
503 MIB->getOperand(0).setReg(HiReg);
504 fixDisp(MIB->getOperand(2));
|
| Mips16InstrInfo.cpp | 91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
94 MIB.addReg(DestReg, RegState::Define);
97 MIB.addReg(SrcReg, getKillRegState(KillSrc));
|
| MipsLongBranch.cpp | 225 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
235 MIB.addReg(MO.getReg());
238 MIB.addMBB(MBBOpnd);
|
| MipsISelLowering.cpp | 781 MachineInstrBuilder MIB;
782 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
787 MIB->getOperand(0).setSubReg(Mips::sub_32);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
784 MIB.addOperand(MI->getOperand(OpNum));
787 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
[all...] |
| ARMBaseRegisterInfo.cpp | 580 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
584 AddDefaultCC(MIB);
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 182 MachineInstrBuilder MIB =
185 MIB->copyImplicitOps(*MBB.getParent(), &*MBBI);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 301 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
303 MIB.addOperand(Cond[i]);
304 MIB.addMBB(TBB);
308 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
310 MIB.addOperand(Cond[i]);
311 MIB.addMBB(TBB);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 226 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
228 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
|
| /external/llvm/lib/CodeGen/ |
| PostRASchedulerList.cpp | 454 MachineInstrBuilder MIB(MF, MI);
457 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
|
| TailDuplication.cpp | 462 MachineInstrBuilder MIB(*FromBB->getParent(), II);
510 MIB.addReg(SrcReg).addMBB(SrcBB);
522 MIB.addReg(Reg).addMBB(SrcBB);
[all...] |
| IfConversion.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 841 MachineInstrBuilder MIB =
844 MIB.addReg(RetRegs[i], RegState::Implicit);
[all...] |
| X86FrameLowering.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| PPCFrameLowering.cpp | 418 MachineInstrBuilder MIB =
421 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
[all...] |
