1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef MipsISELLOWERING_H 16 #define MipsISELLOWERING_H 17 18 #include "Mips.h" 19 #include "MipsSubtarget.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/Target/TargetLowering.h" 24 #include <deque> 25 #include <string> 26 27 namespace llvm { 28 namespace MipsISD { 29 enum NodeType { 30 // Start the numbering from where ISD NodeType finishes. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 // Jump and link (call) 34 JmpLink, 35 36 // Tail call 37 TailCall, 38 39 // Get the Higher 16 bits from a 32-bit immediate 40 // No relation with Mips Hi register 41 Hi, 42 43 // Get the Lower 16 bits from a 32-bit immediate 44 // No relation with Mips Lo register 45 Lo, 46 47 // Handle gp_rel (small data/bss sections) relocation. 48 GPRel, 49 50 // Thread Pointer 51 ThreadPointer, 52 53 // Floating Point Branch Conditional 54 FPBrcond, 55 56 // Floating Point Compare 57 FPCmp, 58 59 // Floating Point Conditional Moves 60 CMovFP_T, 61 CMovFP_F, 62 63 // FP-to-int truncation node. 64 TruncIntFP, 65 66 // Return 67 Ret, 68 69 EH_RETURN, 70 71 // Node used to extract integer from accumulator. 72 ExtractLOHI, 73 74 // Node used to insert integers to accumulator. 75 InsertLOHI, 76 77 // Mult nodes. 78 Mult, 79 Multu, 80 81 // MAdd/Sub nodes 82 MAdd, 83 MAddu, 84 MSub, 85 MSubu, 86 87 // DivRem(u) 88 DivRem, 89 DivRemU, 90 DivRem16, 91 DivRemU16, 92 93 BuildPairF64, 94 ExtractElementF64, 95 96 Wrapper, 97 98 DynAlloc, 99 100 Sync, 101 102 Ext, 103 Ins, 104 105 // EXTR.W instrinsic nodes. 106 EXTP, 107 EXTPDP, 108 EXTR_S_H, 109 EXTR_W, 110 EXTR_R_W, 111 EXTR_RS_W, 112 SHILO, 113 MTHLIP, 114 115 // DPA.W intrinsic nodes. 116 MULSAQ_S_W_PH, 117 MAQ_S_W_PHL, 118 MAQ_S_W_PHR, 119 MAQ_SA_W_PHL, 120 MAQ_SA_W_PHR, 121 DPAU_H_QBL, 122 DPAU_H_QBR, 123 DPSU_H_QBL, 124 DPSU_H_QBR, 125 DPAQ_S_W_PH, 126 DPSQ_S_W_PH, 127 DPAQ_SA_L_W, 128 DPSQ_SA_L_W, 129 DPA_W_PH, 130 DPS_W_PH, 131 DPAQX_S_W_PH, 132 DPAQX_SA_W_PH, 133 DPAX_W_PH, 134 DPSX_W_PH, 135 DPSQX_S_W_PH, 136 DPSQX_SA_W_PH, 137 MULSA_W_PH, 138 139 MULT, 140 MULTU, 141 MADD_DSP, 142 MADDU_DSP, 143 MSUB_DSP, 144 MSUBU_DSP, 145 146 // DSP shift nodes. 147 SHLL_DSP, 148 SHRA_DSP, 149 SHRL_DSP, 150 151 // DSP setcc and select_cc nodes. 152 SETCC_DSP, 153 SELECT_CC_DSP, 154 155 // Load/Store Left/Right nodes. 156 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 157 LWR, 158 SWL, 159 SWR, 160 LDL, 161 LDR, 162 SDL, 163 SDR 164 }; 165 } 166 167 //===--------------------------------------------------------------------===// 168 // TargetLowering Implementation 169 //===--------------------------------------------------------------------===// 170 class MipsFunctionInfo; 171 172 class MipsTargetLowering : public TargetLowering { 173 public: 174 explicit MipsTargetLowering(MipsTargetMachine &TM); 175 176 static const MipsTargetLowering *create(MipsTargetMachine &TM); 177 178 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 179 180 virtual void LowerOperationWrapper(SDNode *N, 181 SmallVectorImpl<SDValue> &Results, 182 SelectionDAG &DAG) const; 183 184 /// LowerOperation - Provide custom lowering hooks for some operations. 185 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 186 187 /// ReplaceNodeResults - Replace the results of node with an illegal result 188 /// type with new values built out of custom code. 189 /// 190 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 191 SelectionDAG &DAG) const; 192 193 /// getTargetNodeName - This method returns the name of a target specific 194 // DAG node. 195 virtual const char *getTargetNodeName(unsigned Opcode) const; 196 197 /// getSetCCResultType - get the ISD::SETCC result ValueType 198 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 199 200 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 201 202 virtual MachineBasicBlock * 203 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 204 205 struct LTStr { 206 bool operator()(const char *S1, const char *S2) const { 207 return strcmp(S1, S2) < 0; 208 } 209 }; 210 211 protected: 212 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 213 214 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const; 215 216 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const; 217 218 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG, 219 unsigned HiFlag, unsigned LoFlag) const; 220 221 /// This function fills Ops, which is the list of operands that will later 222 /// be used when a function call node is created. It also generates 223 /// copyToReg nodes to set up argument registers. 224 virtual void 225 getOpndList(SmallVectorImpl<SDValue> &Ops, 226 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 227 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 228 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const; 229 230 /// ByValArgInfo - Byval argument information. 231 struct ByValArgInfo { 232 unsigned FirstIdx; // Index of the first register used. 233 unsigned NumRegs; // Number of registers used for this argument. 234 unsigned Address; // Offset of the stack area used to pass this argument. 235 236 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {} 237 }; 238 239 /// MipsCC - This class provides methods used to analyze formal and call 240 /// arguments and inquire about calling convention information. 241 class MipsCC { 242 public: 243 enum SpecialCallingConvType { 244 Mips16RetHelperConv, NoSpecialCallingConv 245 }; 246 247 MipsCC( 248 CallingConv::ID CallConv, bool IsO32, CCState &Info, 249 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv); 250 251 252 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 253 bool IsVarArg, bool IsSoftFloat, 254 const SDNode *CallNode, 255 std::vector<ArgListEntry> &FuncArgs); 256 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, 257 bool IsSoftFloat, 258 Function::const_arg_iterator FuncArg); 259 260 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, 261 bool IsSoftFloat, const SDNode *CallNode, 262 const Type *RetTy) const; 263 264 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, 265 bool IsSoftFloat, const Type *RetTy) const; 266 267 const CCState &getCCInfo() const { return CCInfo; } 268 269 /// hasByValArg - Returns true if function has byval arguments. 270 bool hasByValArg() const { return !ByValArgs.empty(); } 271 272 /// regSize - Size (in number of bits) of integer registers. 273 unsigned regSize() const { return IsO32 ? 4 : 8; } 274 275 /// numIntArgRegs - Number of integer registers available for calls. 276 unsigned numIntArgRegs() const; 277 278 /// reservedArgArea - The size of the area the caller reserves for 279 /// register arguments. This is 16-byte if ABI is O32. 280 unsigned reservedArgArea() const; 281 282 /// Return pointer to array of integer argument registers. 283 const uint16_t *intArgRegs() const; 284 285 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator; 286 byval_iterator byval_begin() const { return ByValArgs.begin(); } 287 byval_iterator byval_end() const { return ByValArgs.end(); } 288 289 private: 290 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, 291 CCValAssign::LocInfo LocInfo, 292 ISD::ArgFlagsTy ArgFlags); 293 294 /// useRegsForByval - Returns true if the calling convention allows the 295 /// use of registers to pass byval arguments. 296 bool useRegsForByval() const { return CallConv != CallingConv::Fast; } 297 298 /// Return the function that analyzes fixed argument list functions. 299 llvm::CCAssignFn *fixedArgFn() const; 300 301 /// Return the function that analyzes variable argument list functions. 302 llvm::CCAssignFn *varArgFn() const; 303 304 const uint16_t *shadowRegs() const; 305 306 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, 307 unsigned Align); 308 309 /// Return the type of the register which is used to pass an argument or 310 /// return a value. This function returns f64 if the argument is an i64 311 /// value which has been generated as a result of softening an f128 value. 312 /// Otherwise, it just returns VT. 313 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, 314 bool IsSoftFloat) const; 315 316 template<typename Ty> 317 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 318 const SDNode *CallNode, const Type *RetTy) const; 319 320 CCState &CCInfo; 321 CallingConv::ID CallConv; 322 bool IsO32; 323 SpecialCallingConvType SpecialCallingConv; 324 SmallVector<ByValArgInfo, 2> ByValArgs; 325 }; 326 protected: 327 // Subtarget Info 328 const MipsSubtarget *Subtarget; 329 330 bool HasMips64, IsN64, IsO32; 331 332 private: 333 334 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const; 335 // Lower Operand helpers 336 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 337 CallingConv::ID CallConv, bool isVarArg, 338 const SmallVectorImpl<ISD::InputArg> &Ins, 339 SDLoc dl, SelectionDAG &DAG, 340 SmallVectorImpl<SDValue> &InVals, 341 const SDNode *CallNode, const Type *RetTy) const; 342 343 // Lower Operand specifics 344 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 345 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 346 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 347 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 348 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 349 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 350 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 351 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 352 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 353 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 354 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 355 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 356 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 357 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 358 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 359 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 360 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 361 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 362 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 363 bool IsSRA) const; 364 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 365 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 366 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 367 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 368 369 /// isEligibleForTailCallOptimization - Check whether the call is eligible 370 /// for tail call optimization. 371 virtual bool 372 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 373 unsigned NextStackOffset, 374 const MipsFunctionInfo& FI) const = 0; 375 376 /// copyByValArg - Copy argument registers which were used to pass a byval 377 /// argument to the stack. Create a stack frame object for the byval 378 /// argument. 379 void copyByValRegs(SDValue Chain, SDLoc DL, 380 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 381 const ISD::ArgFlagsTy &Flags, 382 SmallVectorImpl<SDValue> &InVals, 383 const Argument *FuncArg, 384 const MipsCC &CC, const ByValArgInfo &ByVal) const; 385 386 /// passByValArg - Pass a byval argument in registers or on stack. 387 void passByValArg(SDValue Chain, SDLoc DL, 388 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 389 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 390 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 391 const MipsCC &CC, const ByValArgInfo &ByVal, 392 const ISD::ArgFlagsTy &Flags, bool isLittle) const; 393 394 /// writeVarArgRegs - Write variable function arguments passed in registers 395 /// to the stack. Also create a stack frame object for the first variable 396 /// argument. 397 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC, 398 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const; 399 400 virtual SDValue 401 LowerFormalArguments(SDValue Chain, 402 CallingConv::ID CallConv, bool isVarArg, 403 const SmallVectorImpl<ISD::InputArg> &Ins, 404 SDLoc dl, SelectionDAG &DAG, 405 SmallVectorImpl<SDValue> &InVals) const; 406 407 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 408 SDValue Arg, SDLoc DL, bool IsTailCall, 409 SelectionDAG &DAG) const; 410 411 virtual SDValue 412 LowerCall(TargetLowering::CallLoweringInfo &CLI, 413 SmallVectorImpl<SDValue> &InVals) const; 414 415 virtual bool 416 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 417 bool isVarArg, 418 const SmallVectorImpl<ISD::OutputArg> &Outs, 419 LLVMContext &Context) const; 420 421 virtual SDValue 422 LowerReturn(SDValue Chain, 423 CallingConv::ID CallConv, bool isVarArg, 424 const SmallVectorImpl<ISD::OutputArg> &Outs, 425 const SmallVectorImpl<SDValue> &OutVals, 426 SDLoc dl, SelectionDAG &DAG) const; 427 428 // Inline asm support 429 ConstraintType getConstraintType(const std::string &Constraint) const; 430 431 /// Examine constraint string and operand type and determine a weight value. 432 /// The operand object must already have been set up with the operand type. 433 ConstraintWeight getSingleConstraintMatchWeight( 434 AsmOperandInfo &info, const char *constraint) const; 435 436 std::pair<unsigned, const TargetRegisterClass*> 437 getRegForInlineAsmConstraint(const std::string &Constraint, 438 MVT VT) const; 439 440 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 441 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 442 /// true it means one of the asm constraint of the inline asm instruction 443 /// being processed is 'm'. 444 virtual void LowerAsmOperandForConstraint(SDValue Op, 445 std::string &Constraint, 446 std::vector<SDValue> &Ops, 447 SelectionDAG &DAG) const; 448 449 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 450 451 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 452 453 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 454 unsigned SrcAlign, 455 bool IsMemset, bool ZeroMemset, 456 bool MemcpyStrSrc, 457 MachineFunction &MF) const; 458 459 /// isFPImmLegal - Returns true if the target can instruction select the 460 /// specified FP immediate natively. If false, the legalizer will 461 /// materialize the FP immediate as a load from a constant pool. 462 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 463 464 virtual unsigned getJumpTableEncoding() const; 465 466 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 467 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 468 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 469 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 470 bool Nand = false) const; 471 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 472 MachineBasicBlock *BB, unsigned Size) const; 473 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 474 MachineBasicBlock *BB, unsigned Size) const; 475 }; 476 477 /// Create MipsTargetLowering objects. 478 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM); 479 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM); 480 } 481 482 #endif // MipsISELLOWERING_H 483
