| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 229 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
230 OutMI.setOpcode(NewOpc);
413 unsigned NewOpc;
416 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
417 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
418 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
419 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
420 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
421 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
422 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.h | 59 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
|
| MipsInstrInfo.h | 117 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
|
| MipsInstrInfo.cpp | 278 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
|
| MipsLongBranch.cpp | 222 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
223 const MCInstrDesc &NewDesc = TII->get(NewOpc);
|
| MipsSEISelLowering.cpp | 567 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
572 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
|
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 172 int NewOpc;
175 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
176 return NewOpc;
179 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
180 return NewOpc;
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 474 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
475 MI.setDesc(TII.get(NewOpc));
508 unsigned NewOpc = Opcode;
518 NewOpc = immediateOffsetOpcode(Opcode);
530 NewOpc = negativeOffsetOpcode(Opcode);
535 NewOpc = positiveOffsetOpcode(Opcode);
565 if (NewOpc != Opcode)
566 MI.setDesc(TII.get(NewOpc));
599 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
|
| ARMLoadStoreOptimizer.cpp | 776 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
875 unsigned NewOpc = 0;
893 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);
912 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);
930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
939 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| Thumb1RegisterInfo.cpp | 462 unsigned NewOpc = convertToNonSPOpcode(Opcode);
463 if (NewOpc != Opcode && FrameReg != ARM::SP)
464 MI.setDesc(TII.get(NewOpc));
|
| ARMISelDAGToDAG.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelDAGToDAG.cpp | 166 unsigned int NewOpc = AMDGPU::COPY;
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelDAGToDAG.cpp | 166 unsigned int NewOpc = AMDGPU::COPY;
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | [all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 353 unsigned NewOpc = N->getOpcode();
363 NewOpc = ISD::FP_TO_SINT;
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
[all...] |
