| /external/llvm/test/TableGen/ |
| Tree.td | 6 class RegisterClass;
11 def R32 : RegisterClass;
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| TreeNames.td | 6 class RegisterClass;
11 def R32 : RegisterClass;
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| TargetInstrSpec.td | 36 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
58 def VR128 : RegisterClass<[v2i64, v2f64],
64 def REGCLASS : RegisterClass<[], []>;
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| MultiPat.td | 44 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
66 def VR128 : RegisterClass<[v2i64, v2f64],
72 def REGCLASS : RegisterClass<[], []>;
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| Slice.td | 34 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
56 def FR32 : RegisterClass<[f32],
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| cast.td | 35 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
57 def VR128 : RegisterClass<[v2i64, v2f64],
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| /external/jmonkeyengine/engine/src/networking/com/jme3/network/serializing/ |
| Serializer.java | 100 registerClass(boolean.class, new BooleanSerializer());
101 registerClass(byte.class, new ByteSerializer());
102 registerClass(char.class, new CharSerializer());
103 registerClass(short.class, new ShortSerializer());
104 registerClass(int.class, new IntSerializer());
105 registerClass(long.class, new LongSerializer());
106 registerClass(float.class, new FloatSerializer());
107 registerClass(double.class, new DoubleSerializer());
109 registerClass(Boolean.class, new BooleanSerializer());
110 registerClass(Byte.class, new ByteSerializer())
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600RegisterInfo.td | 120 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
131 def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", 0, 127))>;
135 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
138 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
141 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
144 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
147 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
151 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
154 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
157 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32
[all...] |
| SIRegisterInfo.td | 42 def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
89 def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
146 def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
147 def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
148 def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
149 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
152 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
156 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64,
160 def SReg_128 : RegisterClass<"AMDGPU", [v16i8, i128], 128, (add SGPR_128)>;
162 def SReg_256 : RegisterClass<"AMDGPU", [v32i8], 256, (add SGPR_256)>
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.td | 318 def GR8 : RegisterClass<"X86", [i8], 8,
327 def GR16 : RegisterClass<"X86", [i16], 16,
331 def GR32 : RegisterClass<"X86", [i32], 32,
338 def GR64 : RegisterClass<"X86", [i64], 64,
345 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;
348 def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>;
351 def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>;
359 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>;
360 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
361 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.td | 67 def GPR32 : RegisterClass<"AArch64", [i32], 32,
71 def GPR64 : RegisterClass<"AArch64", [i64], 64,
75 def GPR32nowzr : RegisterClass<"AArch64", [i32], 32,
79 def GPR64noxzr : RegisterClass<"AArch64", [i64], 64,
86 def tcGPR64 : RegisterClass<"AArch64", [i64], 64,
94 def GPR32wsp : RegisterClass<"AArch64", [i32], 32,
98 def GPR64xsp : RegisterClass<"AArch64", [i64], 64,
105 def Rxsp : RegisterClass<"AArch64", [i64], 64,
109 def Rwsp : RegisterClass<"AArch64", [i32], 32,
140 def FPR8 : RegisterClass<"AArch64", [i8], 8
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUInstructions.td | 96 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
103 class FABS <RegisterClass rc> : AMDGPUShaderInst <
110 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
123 RegisterClass rc> : Pat <
133 RegisterClass vec_class, int sub_idx,
141 RegisterClass elem_class, RegisterClass vec_class,
150 class Vector_Build <ValueType vecType, RegisterClass elemClass> : Pat <
156 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
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| R600GenRegisterInfo.pl | 77 def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
80 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
83 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add
86 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
91 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
94 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
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| SIInstrFormats.td | 47 class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
70 class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
100 class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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| SIGenRegisterInfo.pl | 142 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
146 def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
167 def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
171 def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>;
172 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
173 def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>;
174 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
195 def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64,
285 print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n";
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstructions.td | 96 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
103 class FABS <RegisterClass rc> : AMDGPUShaderInst <
110 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
123 RegisterClass rc> : Pat <
133 RegisterClass vec_class, int sub_idx,
141 RegisterClass elem_class, RegisterClass vec_class,
150 class Vector_Build <ValueType vecType, RegisterClass elemClass> : Pat <
156 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
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| R600GenRegisterInfo.pl | 77 def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
80 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
83 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add
86 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
91 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
94 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
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| SIInstrFormats.td | 47 class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
70 class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
100 class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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| SIGenRegisterInfo.pl | 142 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
146 def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
167 def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
171 def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>;
172 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
173 def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>;
174 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
195 def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64,
285 print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n";
|
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.td | 227 RegisterClass<"Mips", regTypes, 32, (add
244 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
258 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
264 def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
271 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
273 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
282 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
284 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
296 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
299 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>
[all...] |
| MipsCondMov.td | 55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
80 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
88 multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
95 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
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| /external/clang/test/SemaObjC/ |
| super-dealloc-attribute.m | 23 + (void)registerClass:(id)name __attribute((objc_requires_super));
47 + (void)registerClass:(id)name {} // expected-warning {{method possibly missing a [super registerClass:] call}}
83 + (void)registerClass:(id)name {
84 [super registerClass:name]; // no-warning
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.td | 177 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
181 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
188 def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>;
189 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>;
198 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
200 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
202 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
207 def CRBITRC : RegisterClass<"PPC", [i32], 32,
220 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
226 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)>
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 192 def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
208 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
218 def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
230 def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>;
236 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
245 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
248 def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
254 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> {
262 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
271 def SPR : RegisterClass<"ARM", [f32], 32, (add (decimat
[all...] |
| /external/jmonkeyengine/engine/src/test/jme3test/network/ |
| TestMessages.java | 68 Serializer.registerClass(PingMessage.class);
69 Serializer.registerClass(PongMessage.class);
|
